- 您现在的位置：买卖IC网 > PDF目录180046 > LUCL9219GAR-DT Low-Cost Line Interface with Reverse Battery and Dual Current Limit PDF资料下载
参数资料
| 型号： | LUCL9219GAR-DT |
| 英文描述： | Low-Cost Line Interface with Reverse Battery and Dual Current Limit |
| 中文描述： | 低成本线接口，具有反向电池和双电流限制 |
| 文件页数： | 7/30页 |
| 文件大小： | 397K |
| 代理商： | LUCL9219GAR-DT |
第1页第2页第3页第4页第5页第6页当前第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页
Agere Systems Inc.
15
Data Sheet
November 2001
with Reverse Battery and Dual Current Limit
L9219A/G Low-Cost Line Interface
Applications
A basic loop start reference circuit, using bused ringing with the L9219 SLIC and the T7504 first-generation codec,
is shown in Figure 11. This circuit is designed for a 200
+ 680 || 0.1 F complex termination impedance and
transhybrid. Transmit gain is set at 0 dBm and receive gain is set at –7 dBm.
Figure 11. Basic Loop Start Application Circuit Using T7504-Type Codec
Table 9 shows the design parameters of the application circuit shown in Figure 11. Components that are adjusted
to program these values are also shown.
Table 9. 200
+ 680 || 0.1 F First-Generation Codec Design Parameters
Design Parameter
Parameter Value
Components Adjusted
Loop Closure Threshold
10 mA
RLCTH
dc Loop Current Limit
25 mA
RPROG
2-wire Signal Overload Level
3.14 dBm
—
ac Termination Impedance
200
+ 680 || 0.1 F
RT1, RGP, RRCV, RGP1, RGS, CGS
Hybrid Balance Line Impedance
200
+ 680 || 0.1 F
RHB1
Transmit Gain
0 dBm
RT2, RX, RN1, RN2, CN
Receive Gain
–7 dBm
RRCV, RGP, RT1
RPROG
35.7 k
RLCTH
22.1 k
RPT
50
L7591
RPR
PT
18
1
7
LCTH
8
DCOUT
50
PR
10
RTSP
20
RTS1
402
RTSN
19
RTSN
3.32 M
VRING
VBAT
CF2
11
CF1
12
CF1
0.47
F
AGND
16
BGND
17
IPROG
VBAT
9
CBAT
0.1
F
RCVP
RCVN
5
6
RGP
30.1 k
RT1
71.5 k
RT2
80.6 k
RRCV
137 k
RHB1
357 k
RX
158 k
GSX
VFRO
DX
DR
FSX
FSR
MCLK
1/4 T7504
CODEC
PCM
HIGHWAY
CONTROL
AND
CLOCK
–
+
L9219
SLIC
CRTS1
0.015
F
RTSP
2.94 M
CF2
0.1
F
VBAT
+2.4 V
CB2
0.47
F
22
SUPERVISION
OUTPUTS
B1
B0
14
15
CONTROL
INPUTS
CGN
0.1 nF
RN2
18.2 k
RN1
143 k
NSTAT
B2
13
VITR
23
TXI
24
VTX
25
TG
26
CB
0.1
F
RGP1
8.06 k
RGS
2.37 k
CGS
6.8 nF
TIP
RING
EMR
CB1
0.47
F
VCC
4
VCC
CCC
0.1
F
27
TSD
LCAS
12-3560 (F).g
相关PDF资料 |
PDF描述 |
|---|---|
| LUPXA255A0C200 | 32-BIT, 200 MHz, MICROPROCESSOR, PBGA256 |
| LUPXA255A0C300 | 32-BIT, 300 MHz, MICROPROCESSOR, PBGA256 |
| LV100 | Voltage Transducer LV 100 |
| LV200-AW | Voltage Transducer LV 200-AW/2 |
| LV25-1000 | Voltage Transducer LV 25-1000 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| LUCL9310AP-D | 制造商:AGERE 制造商全称:AGERE 功能描述:Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device |
| LUCL9310AP-DT | 制造商:AGERE 制造商全称:AGERE 功能描述:Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device |
| LUCL9310GP-D | 制造商:AGERE 制造商全称:AGERE 功能描述:Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device |
| LUCL9310GP-DT | 制造商:AGERE 制造商全称:AGERE 功能描述:Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device |
| LUCL9311AP-D | 制造商:AGERE 制造商全称:AGERE 功能描述:Line Interface and Line Access Circuit Full-Feature SLIC with High Longitudinal Balance, Ringing Relay,and GR-909 Test Access |
发布紧急采购，3分钟左右您将得到回复。