参数资料
| 型号： | LV5050NV-TLM-E |
| 厂商： | ON Semiconductor |
| 文件页数： | 6/7页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 20-SSOP |
| 标准包装： | 2,000 |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 1.1MHz |
| 电源电压： | 4.5 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -20°C ~ 85°C |
| 封装/外壳： | 20-LSSOP（0.173"，4.40mm 宽） |
| 包装： | 带卷 (TR) |
LV5050NV
Pin Functions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin name
SW
HDRV
CBOOT
VLIN5
RSNS
NC
ILIM
TD
SS
VIN
CLKO
CT
PGOOD
Description
This Pin is connected with the switching node. A source of an external upper side MOS-FET and a drain of an external lower
side MOS-FET are connected with this pin. This pin becomes the return current path of the HDRV pin. This pin is connected
with a transistor drain of the discharge MOS-FET for SOFT STOP in the IC (typical 15 Ω ). Also, this pin has the signal output
part for the short through prevention of both the upper and lower MOS-FETs.
When this terminal voltage becomes 1V or less for PGND, the LDRV pin is turned on.
The gate drive pin for an external upper side MOS-FET.
The bootstrap capacity connection pin. The gate drive power of upper MOS-FET is provided by this pin.
This pin is connected to the VDD pin through a diode and is connected to the SW pin through the bootstrap capacity.
The output pin of an internal regulator of 5V. the current is provided by the VIN pin.
Also, power supply of the control circuit in the IC is provided by this pin.
Connect an output capacitor of 4.7 μ F between this pin and SGND.
A regulator of 5V operates, even if the IC is in the standby state.
This pin is monitored by an UVLO function and the IC starts by the voltage of 4.0V or more
(the IC is off by the voltage of 3.8V or less.)
The input pin of the over current detection comparator / the current detection amplifier
To detect resistance, this pin is connected to the under side of a resistor for the current detection between the VIN pin and
the DRAIN of the upper MOS-FET. Also, to use the ON resistance of MOS-FET for the current detection, connect this pin to
the SOURCE of the upper MOS-FET. To prevent the common impedance of main current to the detection-voltage, this pin is
connected by independent wiring.
No connection.
The pin to set the trip point for over current detection.
Since the SINK current source of 8.3 μ A (ILIM) is connected in the IC, the over-current detection voltage (ILIM × RLIM) is
generated by connecting a resistor RLIM between this pin and the VIN pin.
The over-current is detected by comparing the voltage between the VIN pin and the ILIM pin to the current detection
resistance RSNS or both end voltage of the upper MOS-FET.
Start-up delay pin.
The time until the IC starts after releasing POR is set by connecting a capacitor between this pin and SGND.
After releasing POR, an external capacitor is charged up by the constant current source of 3.5 μ A in the IC.
When this terminal voltage becomes 2.4V or more, The IC starts. Also, when this terminal voltage
becomes 2.4V or less, The IC becomes the standby state. If external capacitor is not connected,
the IC instantly starts after releasing POR.
The pin to connect a capacitor for soft start. After releasing POR, when the voltage of the TD pin becomes 2.4V or more, the
SS pin is charged by an internal constant current source of 3.5 μ A.
Since this pin is connected to the positive input of the transformer conductance amplifier, the ramp-up wave form of the SS
pin becomes the ramp-up wave form of the output.
During POR operations and after the UV_DELAY time-out, the SS pin is discharged
Power supply pin of the IC
The clock output pin. The clock that synchronized to the oscillation waveform of the CT pin is output.
To synchronize two or more LV5050NVs, the CLKO pin of the device that becomes a master is connected to the CT pin of
the device that becomes a slave. When two or more the devices are synchronized and the start-up timing is changed by
using the Td pin between each device, the earliest start-up device is determined as the master.
The pin to connect an external capacitor for the oscillator. Connect a capacitor between this pin and SGND. When a
capacitor of 130pF is connected between this pin and GND, the oscillation frequency can be set up by 330kHz. Also, this pin
is applied by an external clock signal.
The PWM operation is performed by the frequency of applied clock signal.
When an external clock signal is applied, the rectangular wave of 0V in low level and from 3.3V to 5V in high level is applied.
The rectangular wave source needs the fan-out of 1mA or more.
The power good pin. The open drain MOS-FET of the withstand of 28V is connected in the IC.
When the output voltage of channel 1 is less than -13% for the setup voltage, the low level is output.
This pin has hysteresis of about (VREF × 1.5%).
Continued on next page.
No.A1159-6/7
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| LV5050V-TLM-E | 功能描述:DC/DC 开关控制器 RoHS:否 制造商:Texas Instruments 输入电压:6 V to 100 V 开关频率: 输出电压:1.215 V to 80 V 输出电流:3.5 A 输出端数量:1 最大工作温度:+ 125 C 安装风格: 封装 / 箱体:CPAK |
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