参数资料
| 型号： | LV5052V-TLM-E |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/9页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 30SSOP |
| 标准包装： | 1,000 |
| PWM 型： | 控制器 |
| 输出数： | 2 |
| 频率 - 最大： | 1.1MHz |
| 电源电压： | 9.4 V ~ 16 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -20°C ~ 85°C |
| 封装/外壳： | 30-LSSOP（0.220"，5.60mm 宽） |
| 包装： | 带卷 (TR) |
LV5052V
Continued from preceding page.
Pin No.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Pin name
VIN
CLKO
CT
PGOOD2
SS2
TD2
ILIM2
RSNS2
FB2
COMP2
SGND
CBOOT2
SW2
HDRV2
LDRV2
PGND
Description
Power supply pin of the IC.
This pin is observed by the UVLO function and IC starts by 9.0V or more. (After starts, stop by 8.0V or less. )
The clock output pin. The clock that synchronized to the oscillation waveform of the CT pin is output.
To synchronize two or more LV5052Vs, the CLKO pin of the device that becomes a master is connected to the CT pin of the
device that becomes a slave. When two or more the devices are synchronized and the start-up timing is changed by using
the TD pin between each device, the earliest start-up device is determined as the master.
The pin to connect an external capacitor for the oscillator. Connect a capacitor between this pin and SGND. When a
capacitor of 130pF is connected between this pin and GND, the oscillation frequency can be set up by 330kHz. Also, this
pin is applied by an external clock signal.
The PWM operation is performed by the frequency of applied clock signal.
When an external clock signal is applied, the rectangular wave of 0V in low level and from 0V / 3.3V to 5V in high level is
applied. The rectangular wave source needs the fan-out of 1mA or more.
The power good pin of channel 2.
The pin to connect a capacitor for soft start of channel 2.
Start-up delay pin of channel 2.
The pin to set the trip point for over current detection of channel 2.
Channel 2 side input pin of the over current detection comparator / the current detection amplifier.
Feed back input pin of channel 2.
The phase compensation pin of channel 2.
The system ground of the IC. The reference voltage is generated based on this pin.
This pin is connected to the power supply system ground.
The bootstrap capacity connection pin of channel 2.
This pin is connected with the switching node of channel 2.
The gate drive pin for an external upper side MOS-FET of channel 2.
The gate drive pin of an external lower-side MOS-FET of channel 2.
Power ground pin. This pin becomes the return current path of the LDRV pin.
No.A1394-7/9
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