参数资料
型号: LV8162TT
厂商: SANYO SEMICONDUCTOR CO LTD
元件分类: 运动控制电子
英文描述: BRUSH DC MOTOR CONTROLLER, 0.7 A, PDSO12
封装: 0.150 INCH, MSOP-12
文件页数: 4/7页
文件大小: 221K
代理商: LV8162TT
LV8162TT
No.A1978-4/8
Application Circuit Example
*1 [Power stabilization capacitor]
Be sure to use the power stabilization capacitor with a capacitance of 1F or higher. It cannot be removed.
The VCC and GND are connected using a pattern that is think and short as possible.
When a reverse-connection breakdown prevention diode is used and the supply voltage rises due to a coil kickback or
other cause, increase the capacitance of the capacitor or use a zener diode between the power supply and GND to ensure
that the absolute maximum rating is not exceeded.
This IC performs synchronous rectification for reducing heat generation and improving efficiency. The synchronous
rectification can return the current to the power supply side under certain operating conditions.
When the output duty drops suddenly
When the PWM input frequency is low
The amount of increase in the supply voltage varies depending on whether a reverse-connection breakdown prevention
diode is used, on the size of the power supply capacitor, and fan type, and so rhese factoes must be fully taken into
consideration.
When the supply voltage rises, in the same way as above, increase the capacitance of the capacitor or use a zener diode
between the power supply and GND to ensure that the absolute maximum rating is not exceeded.
*2 [HB pin]
Constant-voltage output pin. This is used for Hall element bias purposes.
If the HB pin is not needed because the bias current to the Hall element is supplied from the power supply, pull this pin
down to GND with a resistor of about 1k.
The power supply bias and HB pin bias cannot be used at the same time.
To adjust the amplitude of the Hall element, insert a resistor between the Hall element and GND.
*3 [IN1 and IN2 pins]
Hall element signal input pin.
The wiring must be made as short as possible to prevent carring of noise.
If noise is carried, insert a capacitor between IN1 and IN2 pins.
The Hall input level must satisfy the following condition:
Difference voltage between IN1 and IN2 > Operating voltage / Hall amplifier gain + Hall amplifier input offset.
1 IN1
2 HB
3 IN2
4 OUT1
5 (NC)
6 GND
12
RD
11
FG
10
PWM
9
VCC
8
(NC)
7
OUT2
H
RDOUT
FGOUT
PWMIN
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