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参数资料
| 型号： | LX1801CLQ |
| 厂商： | MICROSEMI CORP |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC16 |
| 封装： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MLPQ-16 |
| 文件页数： | 7/12页 |
| 文件大小： | 255K |
| 代理商： | LX1801CLQ |
LX1801
PRODUCTION DATA SHEET
Microsemi
Integrated Products Division
11861 Western Avenue, Garden Grove, CA. 92841, 714-898-8121, Fax: 714-893-2570
Page 4
Copyright
2005
Rev. 1.0, 5/4/2006
WWW
.Microse
m
i
.CO
M
SMBus to Analog & Digital System Interface
TM
ELECTRICAL CHA RACTERISTICS
Unless otherwise specified, the following specifications apply over the operating ambient temperature -40
°C
≤ T
A ≤ 85°C except where
otherwise noted and the following test conditions: VDD = 5V + 10 / -5%.
LX1801
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
POWER SUPPLY
Operating Supply Voltage
VDD
4.5
5.5
V
Average Supply Current
IDD
DAC = FFH; idle ADC
1.0
2.5
4.0
mA
BRIGHTNESS CONTROL DAC DC PERFORMANCE
Resolution
8
Bits
Integral Nonlinearity
INL
CODE = 0 to 255, -10nA < IOUT < 10nA
-9
9
LSB
Differential Nonlinearity
DNL
CODE = 0 to 255, -10nA < IOUT < 10nA
-2
5
LSB
Full Scale Output Voltage
FSV
CODE = 255, -10nA < IOUT < 10nA
97% *
VREF
103% *
VREF
V
Offset Error
CODE = 0, -10nA < IOUT < 10nA
-3
4
LSB
Gain Error
-10nA < IOUT < 10nA
-4
2
3
% of
Ideal
LOW LIMIT CLAMP DAC DC PERFORMANCE
Resolution
8
Bits
Relative Accuracy (Note 1)
Low Limit DAC CODE = 15 to 205, High Limit DAC
CODE > 50 LSB above Low Limit DAC CODE
-10
7
LSB
Offset Error
Low Limit DAC CODE = 0, High Limit DAC CODE >
50 LSB above Low Limit DAC CODE
-1
12
LSB
HIGH LIMIT CLAMP DAC DC PERFORMANCE
Resolution
8
Bits
Relative Accuracy (Note 2)
High Limit DAC CODE = 50 to 232, Low Limit DAC
CODE = 50 LSB below High Limit DAC CODE
-7
7
LSB
ALS MODE ACCURACY
Output Error at BRITE_OUT
Low Limit DAC CODE = 15 to 205, High Limit DAC
Code > 50 LSB above Low Limit DAC CODE,
ALS_IN = 20% * VREF to 80% * VREF. VBOT = 0V
3
% of
ALS_IN
ADC
Resolution
8
Bits
Resolvable Input Range
0
VREF
V
Full Scale Output Voltage
FSV
97% *
VREF
103% *
VREF
V
Input Leakage Current (ALS_IN)
I_leak
ALS_IN = 0V to VDD
-1
+1
A
Integral Nonlinearity
INL
Only Major Carry Codes Tested
±3
LSB
Differential Nonlinearity
DNL
Only Major Carry Codes Tested
±1.5
LSB
Offset Error
ALS_IN = 0V
-2
0
2
LSB
Gain Error
ALS_IN = VREF; Read Register. 4
-3
2
3
% of
FSR
REF_IN
Reference Voltage
VREF
1.80
2.040
3.00
V
Input Leakage Current
IREF
-50
0
50
nA
ADR
High Level Input Voltage
VAHL
80
%VDD
Low Level Input Voltage
VALL
20
%VDD
Input Leakage Current
IADR
-50
0
50
nA
SCL, SDA, PWM
High Level Input Voltage
VSHL
2.1
V
Low Level Input Voltage
VSLL
0.8
V
Input Leakage Current
ISMB
-5
0
1
A
SDA Low Level Output Voltage
VOL
IOUT = 3mA
0.4
V
SMBUS
SMB clock frequency
FCLK
10
100
KHz
Note 1: The Relative Accuracy of the Low Limit DAC is specified to be the deviation from the ideal programmed value: Ideal = VREF * (CODE/255).
The Relative Accuracy is specified for the range CODE = 15 to 205
Note 2: The Relative Accuracy of the High Limit DAC is specified to be the deviation from the ideal programmed value: Ideal = VREF * (CODE/255).
The Relative Accuracy is specified for the range CODE = 50 to 232
EE
LL
EE
CC
TT
RR
IICC
AA
LL
SS
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