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参数资料
| 型号： | LXT363QE |
| 英文描述： | PCM TRANSCEIVER|SINGLE|T-1(DS1)|CMOS|QFP|44PIN|PLASTIC |
| 中文描述： | 的PCM收发器|单|的T 1（DS1的）|的CMOS | QFP封装| 44PIN |塑料 |
| 文件页数： | 26/52页 |
| 文件大小： | 1187K |
| 代理商： | LXT363QE |
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LXT361
—
Integrated T1/E1 LH/SH Transceiver for DS1/DSX-1 or PRI Applications
26
Datasheet
4.0
Register Definitions
The LXT361 contains five read/write and three read-only registers.
Table 5
lists the LXT361
register addresses. Note that only bits A6 through A1 of the address byte are valid; the address
decoder ignores bits A7 and A0.
Table 6
identifies the name of each register bit.
Table 7
through
Table 15
describe the function of the bits in each register.
Note: upon power-up or reset, all registers are cleared to 0.
Table 5. Register Addresses
Register
Address
1
A7 - A0
Name
Abbr
Control #1
CR1
x010000x
Control #2
CR2
x010001x
Control #3
CR3
x010010x
Interrupt Clear
ICR
x010011x
Transition Status
TSR
x010100x
Performance Status
PSR
x010101x
Equalizer Status
ESR
x010110x
Control #4
CR4
x010111x
1. x = don
’
t care.
Table 6. Register and Bit Summary
Register
Bit
Name
Type
7
6
5
4
3
2
1
0
Control #1
CR1
R/W
JASEL1
JASEL0
ENCENB
UNIENB
EC4
EC3
EC2
EC1
Control #2
CR2
R/W
RESET
EPAT1
EPAT0
ETAOS
ENLOOP
EALOOP
ELLOOP
ERLOOP
Control #3
CR3
R/W
JA6HZ
PCLKE
SBIST
EQZMON
reserved
1
ES64
ESCEN
ESJAM
Interrupt Clear
ICR
R/W
CESU
CESO
CDFMO
reserved
2
CQRSS
CAIS
CNLOOP
CLOS
Transition
Status
TSR
R
ESUNF
ESOVR
TDFMO
reserved
1
TQRSS
TAIS
TNLOOP
TLOS
Performance
Status
PSR
R
reserved
1
BIST
DFMO
reserved
1
QRSS
AIS
NLOOP
LOS
Equalizer
Status
ESR
R
LATN7
LATN6
LATN5
LATN4
reserved
1
reserved
1
reserved
1
reserved
1
Control #4
CR4
R/W
reserved
1
reserved
1
reserved
1
reserved
1
COL32CM
LOS2048
ZEROV
CODEV
1. In writable registers, bits labeled
reserved
should be set to 0 (except as in note 2 below) for normal operation and ignored in
read only registers.
2. Write a 1 to this bit for normal operation.
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