参数资料
| 型号： | M1A3PE3000-1FG896 |
| 厂商： | Microsemi SoC |
| 文件页数： | 161/162页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 1KB FLASH 3M 896-FBGA |
| 标准包装： | 27 |
| 系列： | ProASIC3E |
| RAM 位总计： | 516096 |
| 输入/输出数： | 620 |
| 门数： | 3000000 |
| 电源电压： | 1.425 V ~ 1.575 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 896-BGA |
| 供应商设备封装： | 896-FBGA（31x31） |
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Pin Descriptions and Packaging
3-2
Revision 13
insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can
be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals
will not be able to transition the device, even in bypass mode.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
VPUMP
Programming Supply Voltage
For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left
floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming
power supply voltage (VPUMP) range is listed in the datasheet.
When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of
oscillation from the charge pump circuitry.
For proper programming, 0.01 F and 0.33 F capacitors (both rated at 16 V) are to be connected in
parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.
Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent
filtering capacitors rather than supplying them from a common rail.
User-Defined Supply Pins
VREF
I/O Voltage Reference
Reference voltage for I/O minibanks. VREF pins are configured by the user from regular I/Os, and any
I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards
require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One
VREF pin can support the number of I/Os available in its minibank.
User Pins
I/O
User Input/Output
The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are
compatible with the I/O standard selected.
During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC
supplies continuously powered up, when the device transitions from programming to operating mode, the
I/Os are instantly configured to the desired user configuration.
Unused I/Os are configured as follows:
Output buffer is disabled (with tristate value of high impedance)
Input buffer is disabled (with tristate value of high impedance)
Weak pull-up is programmed
GL
Globals
GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the
global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have
identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.
See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power
Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide. All
inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an
input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled
GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.
The inputs to the global network are multiplexed, and only one input can be used as a global input.
Refer to the I/O Structure section of the ProASIC3E FPGA Fabric User’s Guide for an explanation of the
naming of global pins.
相关PDF资料 |
PDF描述 |
|---|---|
| A3PE3000-1FG896 | IC FPGA 1KB FLASH 3M 896-FBGA |
| M1A3PE3000-1FGG896 | IC FPGA 1KB FLASH 3M 896-FBGA |
| ASM44DRTH-S13 | CONN EDGECARD 88POS .156 EXTEND |
| EMM44DSAN | CONN EDGECARD 88POS R/A .156 SLD |
| A54SX72A-2FG484I | IC FPGA SX-A 108K 484-FBGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M1A3PE3000-1FG896ES | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| M1A3PE3000-1FG896I | 功能描述:IC FPGA 1KB FLASH 3M 896-FBGA RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3E 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| M1A3PE3000-1FG896PP | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs |
| M1A3PE3000-1FGG324 | 功能描述:IC FPGA 1KB FLASH 3M 324-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3E 产品培训模块:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色产品:Cyclone? IV FPGAs 标准包装:60 系列:CYCLONE® IV GX LAB/CLB数:9360 逻辑元件/单元数:149760 RAM 位总计:6635520 输入/输出数:270 门数:- 电源电压:1.16 V ~ 1.24 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:484-BGA 供应商设备封装:484-FBGA（23x23） |
| M1A3PE3000-1FGG324I | 功能描述:IC FPGA 1KB FLASH 3M 324-FBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:ProASIC3E 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
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