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参数资料
| 型号： | M28C17-90WK1TR |
| 厂商： | 意法半导体 |
| 元件分类： | 保险丝 |
| 英文描述： | Fuses, 8A 250V T IEC GLASS 5X20 |
| 中文描述： | 16千位2K × 8并行EEPROM，带有软件数据保护 |
| 文件页数： | 2/17页 |
| 文件大小： | 131K |
| 代理商： | M28C17-90WK1TR |
M28C16B, M28C17B
2/17
Figure 2A. PLLC Connections
Note: 1. NC = Not Connected
AI02817
N
A8
A9
NC
NC
G
A10
E
D
17
A0
NC
DQ0
D
D
N
D
A6
A5
A4
A3
A2
A1
9
W
1
N
DQ6
A
DQ7
32
N
V
M28C16B
N
D
25
V
Figure 2B. PLLC Connections
Note: 1. NC = Not Connected
AI02830
N
A8
A9
NC
NC
G
A10
E
D
17
A0
NC
DQ0
D
D
N
D
A6
A5
A4
A3
A2
A1
9
W
1
N
DQ6
A
DQ7
32
R
V
M28C17B
N
D
25
V
The M28C17B is like the M28C16B in every way,
except that it has an extra ready/busy (RB) output.
The device has been designed to offer a flexible
microcontroller interface, featuring software hand-
shaking, with Data Polling and Toggle Bit. The de-
vice supports a 64 byte Page Write operation.
Software Data Protection (SDP) is also supported,
using the standard JEDEC algorithm.
SIGNAL DESCRIPTION
The external connections to the device are sum-
marized in Table 1, and their use in Table 3.
Addresses (A0-A10).
The address inputs are
used to select one byte from the memory array
during a read or write operation.
Data In/Out (DQ0-DQ7).
The contents of the data
byte are written to, or read from, the memory array
through the Data I/O pins.
Chip Enable (E).
The chip enable input must be
held low to enable read and write operations.
When Chip Enable is high, power consumption is
reduced.
Output Enable (G).
The Output Enable input con-
trols the data output buffers, and is used to initiate
read operations.
Write Enable (W).
The Write Enable input controls
whether the addressed location is to be read, from
or written to.
Ready/Busy (RB).
Ready/Busy (on the M28C17B
only) is an open drain output that can be used to
detect the end of the internal write cycle.
DEVICE OPERATION
In order to prevent data corruption and inadvertent
write operations, an internal V
CC
comparator in-
hibits the Write operations if the V
CC
voltage is
lower than V
WI
(see Table 4A). Once the voltage
applied on the V
CC
pin goes over the V
WI
thresh-
old (V
CC
>V
WI
), write access to the memory is al-
lowed after a time-out t
PUW
, as specified in Table
4A.
Further protection against data corruption is of-
fered by the E and W low pass filters: any glitch,
on the E and W inputs, with a pulse width less than
10 ns (typical) is internally filtered out to prevent
inadvertent write operations to the memory.
Read
The device is accessed like a static RAM. When E
and G are low, and W is high, the contents of the
addressed location are presented on the I/O pins.
Otherwise, when either G or E is high, the I/O pins
revert to their high impedance state.
Write
Write operations are initiated when both W and E
are low and G is high. The device supports both
W-controlled and E-controlled write cycles (as
shown in Figure 11 and Figure 12). The address is
latched during the falling edge of W or E (which
ever occurs later) and the data is latched on the
rising edge of W or E (which ever occurs first). Af-
ter a delay, t
WLQ5H
, that cannot be shorter than the
value specified in Table 10A, the internal write cy-
cle starts. It continues, under internal timing con-
trol, until the write operation is complete. The
commencement of this period can be detected by
reading the Page Load Timer Status on DQ5. The
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