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参数资料
| 型号： | M28C17-90WK1TR |
| 厂商： | 意法半导体 |
| 元件分类： | 保险丝 |
| 英文描述： | Fuses, 8A 250V T IEC GLASS 5X20 |
| 中文描述： | 16千位2K × 8并行EEPROM，带有软件数据保护 |
| 文件页数： | 4/17页 |
| 文件大小： | 131K |
| 代理商： | M28C17-90WK1TR |
M28C16B, M28C17B
4/17
Table 3. Operating Modes
1
Note: 1. 0=
V
IL
; 1=
V
IH
; X =
V
IH
or V
IL
; V=12V ± 5%.
Mode
E
G
W
DQ0-DQ7
Stand-by
1
X
X
Hi-Z
Output Disable
X
1
X
Hi-Z
Write Disable
X
X
1
Hi-Z
Read
0
0
1
Data Out
Write
0
1
0
Data In
Chip Erase
0
V
0
Hi-Z
end of the cycle can be detected by reading the
status of the Data Polling and the Toggle Bit func-
tions on DQ7 and DQ6.
Page Write
The Page Write mode allows up to 64 bytes to be
written on a single page in a single go. This is
achieved through a series of successive Write op-
erations, no two of which are separated by more
than the t
WLQ5H
value (as specified in Table 10A).
The page write can be initiated during any byte
write operation. Following the first byte write in-
struction the host may send another address and
data with a minimum data transfer rate of:
1/t
WLQ5H
.
The internal write cycle can start at any instant af-
ter t
WLQ5H
. Once initiated, the write operation is in-
ternally timed, and continues, uninterrupted, until
completion.
All bytes must be located on the same page ad-
dress (A10-A6 must be the same for all bytes).
Otherwise, the Page Write operation is not execut-
ed.
As with the single byte Write operation, described
above, the DQ5, DQ6 and DQ7 lines can be used
to detect the beginning and end of the internally
controlled phase of the Page Write cycle.
Software Data Protection (SDP)
The device offers a software-controlled write-pro-
tection mechanism that allows the user to inhibit all
write operations to the device. This can be useful
for protecting the memory from inadvertent write
cycles that may occur during periods of instability
(uncontrolled bus conditions when excessive
noise is detected, or when power supply levels are
outside their specified values).
By default, the device is shipped in the “unprotect-
ed” state: the memory contents can be freely
changed by the user. Once the Software Data Pro-
tection Mode is enabled, all write commands are
Table 4A. Power-Up Timing
1
for M28CxxB (5V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; V
CC
= 4.5 to 5.5 V)
Symbol
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing
1
for M28CxxB-W (3V range)
(T
A
= 0 to 70 °C or -40 to 85 °C; V
CC
= 2.7 to 3.6 V)
Symbol
Note: 1. Sampled only, not 100% tested.
Parameter
Min.
Max.
Unit
t
PUR
Time Delay to Read Operation
1
μs
t
PUW
Time Delay to Write Operation (once V
CC
≥
V
WI
)
10
ms
V
WI
Write Inhibit Threshold
3.0
4.2
V
Parameter
Min.
Max.
Unit
t
PUR
Time Delay to Read Operation
1
μs
t
PUW
Time Delay to Write Operation (once V
CC
≥
V
WI
)
15
ms
V
WI
Write Inhibit Threshold
1.5
2.5
V
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