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参数资料
| 型号： | M29F400FB5AN6F2 |
| 元件分类： | PROM |
| 英文描述： | 256K X 16 FLASH 5V PROM, 55 ns, PDSO48 |
| 封装： | 12 X 20 MM, ROHS COMPLIANT, PLASTIC, TSOP1-48 |
| 文件页数： | 15/65页 |
| 文件大小： | 1669K |
| 代理商： | M29F400FB5AN6F2 |
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Bus Operations
M29FxxxFT, M29FxxxFB
22/65
3
Bus Operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write
Enable are ignored by the memory and do not affect bus operations.
3.1
Bus Read.
Bus Read operations read from the memory cells, or specific registers in the Command
Interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Read Mode AC Waveforms, and Table Table 15., Read AC Characteristics, for details of
when the output becomes valid.
3.2
Bus Write.
Bus Write operations write to the Command Interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figures Figure 20. and Figure 21., Write AC
timing requirements.
3.3
Output Disable.
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH.
3.4
Standby.
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to
the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see Table Table 14., DC Characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply Current, ICC3, for Program or Erase operations until the operation completes.
3.5
Automatic Standby.
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or
more the memory enters Automatic Standby where the internal Supply Current is reduced to
the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus
Read operation is in progress.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M29F400FT55M32 | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE 5V - Trays |
| M29F400FT55M3E2 | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE 5V - Trays 制造商:Micron Technology Inc 功能描述:IC FLASH 4MBIT 55NS 44SO |
| M29F400FT55M3F2 | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE 5V - Trays |
| M29F400FT55M3F2 TR | 制造商:Micron Technology Inc 功能描述:IC FLASH 4MBIT 55NS 44SO |
| M29F400FT55M3T2 | 制造商:Micron Technology Inc 功能描述:AUTOMOTIVE 5V - Trays |
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