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参数资料
型号： M30100M6T-XXXFP
元件分类： 微控制器/微处理器
英文描述： 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP32
封装： 7 X 7 MM, 0.80 MM PITCH, PLASTIC, LQFP-32
文件页数： 125/163页
文件大小： 1678K
代理商： M30100M6T-XXXFP
Under
development
Tentative Specifications REV.E
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M30100/M30102 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Timer X
64
(1) Timer mode
In this mode, the timer counts an internally generated count source. (See Table 1.14.3) Figure 1.14.6
shows the Timer X mode register in timer mode.
Item
Specification
Count source
f1, f8, f32, fC32
Count operation
Down count
When the timer underflows, it reloads the reload register contents before continuing
counting
Divide ratio
1/(n+1)/(m+1) n : Set value of Prescaler X, m: Set value of Timer X
Count start condition
Count start flag is set (=1)
Count stop condition
Count start flag is reset (=0)
Interrupt request generation timing When Timer X underflows [Timer X interruption]
CNTR0 pin function
Programmable I/O port, or CNTR0 interrupt input pin
TXOUT pin function
Programmable I/O port
Read from timer
Count value can be read out by reading Timer X register.
Same applies to Prescaler X register.
Write to timer
When a value is written to Timer X register, it is written to both reload register and counter.
Same applies to Prescaler X register.
Table 1.14.3. Specifications of timer mode
Timer X mode register
Symbol
Address
When reset
TXMR
008B16
000000002
Bit name
Function
Bit symbol
W
R
b7 b6 b5 b4 b3 b2 b1 b0
0 0 : Timer mode
b1 b0
TXMOD2
TXS
TXMOD1
R0EDG
TXMOD0
TXOCNT
Invalid in timer mode.
When write, set "0". When read, this contents is indeteminate.
Operation mode
select bit 0, 1
Timer X count
start flag
0 : Stops counting
1 : Starts counting
0 : In timer mode, set to "0"
0
0 : In timer mode, set to "0"
CNTR0 polarity
switching bit
0 : Rising edge
1 : Falling edge
0
(Note 1)
Note 1: This bit should rewrite with inhibiting the CNTR0 interrupt.
TXEDG
TXUND
Invalid in timer mode.
When write, set "0". When read, this contents is indeteminate.
Figure 1.14.6. Timer X mode register in timer mode
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