M306H5MG-XXXFP/MC-XXXFP/FGFP
Rev.1.20
Dec 13, 2005
page 247 of 323
REJ03B0095-0100Z
Pin name
Connection
Ports P0 to P7, P80 to P84,
P86 to P87, P9 to P10
XOUT (Note 4)
AVSS, VREF, BYTE
AVCC
After setting for input mode, connect every pin to VSS via a resistor(pull-down);
or after setting for output mode, leave these pins open. (Note 1, 2 ,3)
Open
Connect to VCC
Connect to VSS
NMI (P85)
Connect via resistor to VCC (pull-up)
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 4: With external clock input to XIN pin.
Table 2.15.1. Unassigned Pin Handling in Single-chip Mode
Pin name
Connection
AVSS, VREF
AVCC
Open
Connect to VCC
Connect to VSS
HOLD, RDY, NMI (P85)
Connect via resistor to VCC (pull-up)
BHE, ALE, HLDA,
XOUT (Note 5), BCLK (Note 6)
P45 / CS1 to P47 / CS3
Connect to VCC via a resistor (pulled high) by setting the PD4 register’s
corresponding direction bit for CSi (i=1 to 3) to “0” (input mode) and the
CSR register’s CSi bit to “0” (chip select disabled).
Ports P0 to P7, P80 to P84,
P86 to P87, P9 to P10
After setting for input mode, connect every pin to VSS via a resistor (pull-down);
or after setting for output mode, leave these pins open. (Note 1, 2, 3, 4)
Note 1: When setting the port for output mode and leave it open, be aware that the port remains in input mode until
it is switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes
indeterminate, causing the power supply current to increase while the port remains in input mode.
Furthermore, by considering a possibility that the contents of the direction registers could be changed by
noise or noise-induced runaway, it is recommended that the contents of the direction registers be
periodically reset in software, for the increased reliability of the program.
Note 2: Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins
(within 2 cm).
Note 3: If the CNVSS pin has the VSS level applied to it, these pins are set for input ports until the processor mode
is switched over in a program after reset. For this reason, the voltage levels on these pins become
indeterminate, causing the power supply current to increase while they remain set for input ports.
Note 4: When the ports P70 and P71 are set for output mode, make sure a low-level signal is output from the pins.
The ports P70 and P71 are N-channel open-drain outputs.
Note 5: With external clock input to XIN pin.
Note 6: If the PM07 bit in the PM0 register is set to “1” (BCLK not output), connect this pin to VCC via a resistor
(pulled high).
Table 2.15.2. Unassigned Pin Handling in Memory Expansion Mode and Microprocessor Mode