M306H5MG-XXXFP/MC-XXXFP/FGFP
Rev.1.20
Dec 13, 2005
page 182 of 323
REJ03B0095-0100Z
2.14.4 CRC Operation Circuit (EPG-J)
CRC operation circuit (EPG-J) is a circuit for performing error detection and error correction by the
272-190 shortening difference set cyclic code which is a coding system in a data multiplex broadcast.
CRC register consists of registers shown in Figure 2.14.5. CRC register can perform error detection
and error correction by majority logic by setting up a generator polinomial, code data, etc. CRC
register composition is shown in Table 2.14.3.
Table 2.14.3 CRC register composition
CA3 to CA0
0016
0116
0216
0316
0416
0516
0616
0716
0816
0916
0A16
0B16
0C16
0D16
CD15
DAOUT15
_
CRC_66
CRC_50
CRC_34
CRC_18
CRC_02
_
CD14
DAOUT14
_
CRC_67
CRC_51
CRC_35
CRC_19
CRC_03
_
CD13
DAOUT13
_
CRC_36
CRC_20
CRC_04
_
CD12
DAOUT12
_
CRC_37
CRC_21
_
CD11
DAOUT11
_
CRC_38
CRC_22
_
CD10
DAOUT10
CRC_ERR10
CRC_39
CRC_23
_
CD9
DAOUT9
CRC_ERR09
CRC_40
CRC_24
CRC_08
_
CD8
DAOUT8
CRC_ERR08
CRC_41
CRC_25
CRC_09
_
CD7
DAOUT7
CRC_ERR07
CRC_74
CRC_58
CRC_42
CRC_26
CRC_10
_
CD6
DAOUT6
CRC_ERR06
CRC_75
CRC_59
CRC_43
CRC_27
CRC_11
_
CD5
DAOUT5
CRC_ERR05
CRC_44
CRC_28
CRC_12
_
CD4
DAOUT4
CRC_ERR04
CRC_45
CRC_29
CRC_13
_
CD3
DAOUT3
CRC_ERR03
CRC_46
CRC_30
CRC_14
_
CD2
DAOUT2
CRC_ERR02
CRC_47
CRC_31
CRC_15
_
CD1
DAOUT1
CRC_ERR01
CRC_48
CRC_32
CRC_16
CRC_00
CD0
DAOUT0
CRC_ERR00
CRC_49
CRC_33
CRC_17
CRC_01
Remarks
CRC_68
CRC_52
CRC_69
CRC_53
CRC_54
CRC_55
CRC_70
CRC_71
CRC_72
CRC_56
CRC_73
CRC_57
CRC_76
CRC_60
CRC_77
CRC_61
CRC_78
CRC_62
CRC_79
CRC_63
CRC_80
CRC_64
CRC_81
CRC_65
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
__
_
CRC_05
CRC_06
CRC_07
Symbol
address
at Reset
CA
021216
000016
Symbol
address
at Reset
CD
021416
000016
b15
b5
b7
b0
CRC register address control register
CRC register data control register
W
R
Specify accessing CRC register address.
Function
The value which
can be set up
0016 to 0D16
0016 to 3F16
Notes 1: When access to CRC register, must be set CRC register address at first, then use
CRC register data control register (021416).
Notes 2: When bit 4 = "0" setting, CRC register data control register increments by accessing
CRC register data control register, so it is not neccesary to setting the next CRC
register address. When bit 4 = "1" setting, the address is fixed.
Notes 3: When bit 15 = "0" setting, the value of a CRC data register
(address (CA3 to CA0) =01 to 07) is cleared.
b15
b 8b7
b0
W
R
Write and read out the data of CRC register which is
specified by CRC register address control register
(address 021216)
b3
Nothing is assigned.
When write, set to "0." When read, its content is determinate.
– –
CRC register address automatic increment.
0: enable / 1 : disable (Notes 2)
–
b4
b14 b13
b8
CRCLOOP 0 to 5
The number of times of a CRC
operation repetition.
CRCCHANGE
Error detection / error correction
Selection setting
0:error detection mode / 1: Error correction mode
–
CRCON
CRC operation
0: Stop/1 : Operation (Note 3)
–
000016 to FFFF16
Note: Data access must be 16-bit unit. 8-bit unit access is disable.
Function
The value which
can be set up
Figure 2.14.5 Composition of CRC register access related register