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参数资料
| 型号： | M34506M2-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| 封装： | 5.30 X 12.60 MM, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件页数： | 32/114页 |
| 文件大小： | 836K |
| 代理商： | M34506M2-XXXFP |
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1
1-7
OVERVIEW
32180 Group User’s Manual (Rev.1.0)
Table 1.2.1 Features of the 32180 (2/2)
1.2 Block Diagram
Functional Block
Features
A-D converter (ADC)
16 channels: 10-bit resolution A-D converter × 2 blocks
Conversion modes: Ordinary conversion modes plus comparator mode
Operation modes: Single conversion mode and n-channel scan mode (n = 1–16)
Sample-and-hold function: Sample-and-hold function can be enabled or disabled as necessary.
A-D disconnection detection assist function: Influences of the analog input voltage wrapping
around from any preceding channel during scan mode operation are suppressed.
An inflow current bypass circuit is built-in.
Can generate an interrupt or start DMA transfer upon completion of A-D conversion.
Either 8 or 10-bit conversion results can be read out.
Interrupt request: Completion of A-D conversion
DMA transfer request: Completion of A-D conversion
Serial I/O (SIO)
6-channel serial I/O
Can be chosen to be clock-synchronized serial I/O or UART.
Data can be transferred at high speed (2 Mbits per second during clock-synchronized mode or
156 Kbits per second during UART mode when f(BCLK) = 20 MHz).
Interrupt request: Reception completed, receive error, transmit buffer empty or transmission completed
DMA transfer request: Reception completed or transmit buffer empty
CAN
16 message slots × 2 blocks
Compliant with CAN specification 2.0B active.
Interrupt request: Transmission completed, reception completed, bus error, error-passive, bus-off
or single shot
DMA transfer request: Failed to send, transmission completed or reception completed
Real-Time Debugger
Internal RAM can be rewritten or monitored independently of the CPU by entering a command
(RTD)
from the outside.
Comes with exclusive clock-synchronized serial ports.
Interrupt request: RTD interrupt command input
Interrupt Controller (ICU)
Controls interrupt requests from the internal peripheral I/O.
Supports 8-level interrupt priority including an interrupt disabled state.
External interrupt: 35 sources (SBI# and TIN0–TIN33)
TIN pin input sensing: Rising, falling or both edges or high or low level
Wait Controller
Controls wait states for access to the extended external area.
Insertion of 0–7 wait states by setting up in software + wait state extension by entering WAIT# signal
PLL
A multiply-by-8 clock generating circuit
Clock
Maximum external input clock frequency (XIN) is 10.0 MHz. (Note 1)
CPUCLK: Operating clock for the M32R-FPU core, internal flash memory and internal RAM
The maximum CPU clock is 80 MHz (when f(XIN) = 10 MHz).
BCLK: Operating clock for the internal peripheral I/O and external data bus
The maximum peripheral clock is 20 MHz (peripheral module access when
f(XIN) = 10 MHz).
Clock output (BCLK pin output): A clock with the same frequency as BCLK is output from this pin.
JTAG
Boundary scan function
VDC
Internal power supply generating circuit: Generates the internal power supply (2.5 V) from an
external single power supply (5 or 3.3 V).
Ports
Input/output pins: 158 pins
The port input threshold can be set in a program to one of three levels individually for each port
group (with or without Schmitt circuit, selectable).
Note 1: The maximum external input clock frequency (XIN) for the M32180F8VFP is 8.0 MHz.
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相关代理商/技术参数 |
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|---|---|
| M34506M4 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34506M4-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES |
| M34507E4FP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
| M34507M2-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:4-BIT CISC SINGLE-CHIP MICROCOMPUTER 4500 SERIES |
| M34507M4-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER |
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