参数资料
型号: M34519E8FP
元件分类: 微控制器/微处理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
封装: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件页数: 25/50页
文件大小: 1808K
代理商: M34519E8FP
31
9571B–AT42–08/10
AT42QT1111-MU/AT42QT1111-AU
7.6
Address 2: Detect Integrator Limit (DIL)/Drift Hold Time (DHT)
DIL: the detection integrator (DI) limit. To suppress false detections caused by spurious events
like electrical noise, the device incorporates a DI counter mechanism. A per-key counter is
incremented each time the channel has exceeded its threshold and stayed there for a number of
acquisitions in succession, without going below the threshold level. When this counter reaches a
preset limit the channel is finally declared to be touched. If on any acquisition the delta is not
seen to exceed the threshold level, the counter is cleared and the process has to start from the
beginning. Similarily, when a touch is removed the key is counted out of touch by the DI counter.
Note:
A setting of 0 for DI is invalid; the valid range is 1 to 15.
DHT: the drift hold time. After a key-touch has been removed, the QT1111 pauses in the
implementation of its “Drift” compensation for a time. After this time has expired, drift
compensation continues as normal. The drift timer continues from the value at which it was
“paused” at the start of the Drift Hold Time. The Drift Hold Time is a multiple of 160 ms, providing
options from 0 to 2400 ms.
Default DIL value:
3
Default DHT value:
8 (1280 ms)
7.7
Address 3: Positive Threshold (PTHR)/Positive Hysteresis (PHYST)
PTHR: the positive threshold for the signal. If a key signal is significantly higher than the
reference signal, this typically indicates that the calibration data is no longer valid. In other
words, some factor has changed since the calibration was carried out, thus rendering it invalid.
Generally this is compensated for by the drift, but the greater the difference the longer this will
take. In order to speed up this correction, the positive threshold is used: if the positive threshold
is exceeded, the QT1111 (that is, all keys) is recalibrated.
Table 7-4.
Detect Integrator/Drift Hold Time
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
2DIL
DHT
Table 7-5.
Positive Threshold (THR)/Positive Hystereis (HYST)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3
PTHR
PHYST
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