3
MITSUBISHI <DIGITAL ASSP>
M35500AFP/BGP
FLD(VFD) CONTROLLER
Table. 1. Pin description
Function
Apply voltage of 5 V to VCC, and 0 V to VSS.
Applies voltage supplied to pull-down resistors.
RC oscillator pins for system clock.
Reset input pin for active “L”.
Internal pull-up resistors connected between the RESET and VCC pins.
Serial transfer is possible by inputting “L” signal.
Clock for serial transfer is input.
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
Serial data is output.
During reset it is in high-impedance state.
Serial data is input.
Read a clock twice with 2 MHz sampling clock and judge if it is a noise or not.
Pin for ordinary output or digit output.
At reset this port is set to VEE level through a pull-down resistor.
Pin for digit output or segment output.
At reset this port is set to VEE level through a pull-down resistor.
Pin for segment output.
At reset this port is set to VEE level through a pull-down resistor.
Output
N-channel
open-drain
P-channel
open-drain
P-channel
open-drain
P-channel
open-drain
Pin
VCC, VSS
VEE
XIN
XOUT
______
RESET
____
CS
SCLK
SOUT
SIN
DIG0/P0 –
DIG7/P7
DIG8/SEG17 –
DIG17/SEG8
SEG0 – SEG7
Name
Power source
Pull-down
power source
Clock input
Clock output
______
RESET input
Chip select
Serial clock
Serial output
Serial input
Digit/Port
Digit/Segment
Segment
Input
CMOS input
Noise filter
CMOS input
Noise filter
PORT BLOCK
Fig. 3. Port block diagram
PIN DESCRIPTION
(2) Digit pin
latch
VEE
Dimmer signal
(Note)
Shift signal from high-order
Shift signal to low-order
(3) Segment pin
latch
VEE
Dimmer signal
(Note)
Segment data
(6) SIN, SCLK pin
Serial input
Serial clock input
Noise filter
(1) Digit/Port pin
Digit/Segment pin
Data bus
Segment data
latch
VEE
Dimmer signal
(Note)
Shift signal from high-order
Shift signal to low-order
V High-breakdown-voltage P-channel transistor
Note: Dimmer signal is for setting the Toff time.
SOUT signal
(4) SOUT pin
(5) CS pin
CS input
A-D conversion input
(7) A-D input
Noise filter
V