参数资料
型号: M37150EFFP
元件分类: 微控制器/微处理器
英文描述: 8-BIT, OTPROM, 8.95 MHz, MICROCONTROLLER, PDSO42
封装: 0.80 MM PITCH, PLASTIC, SSOP-42
文件页数: 21/62页
文件大小: 880K
代理商: M37150EFFP
25
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(2) Event counter mode [01]
Figure 29 shows the bit configuration of the timer Bi mode register
during event counter mode. In event counter mode, the bit 0 in the
timer Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBiIN pin is counted when the count start
flag is “1” and counting is stopped when it is “0”. Count is per-
formed at the fall of the input signal when bits 2, and 3 are “0” and
at the rise of the input signal when bit 3 is “0” and bit 2 is “1”.
When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and
fall of the input signal.
Data write, data read and timer interrupt are performed in the
same way as for timer mode.
(3) Pulse period measurement/pulse width
measurement mode [10]
Figure 30 shows the bit configuration of the timer Bi mode register
during pulse period measurement/pulse width measurement
mode.
In pulse period measurement/pulse width measurement mode, bit
0 must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select
the clock source. The selected clock is counted when the count
start flag is “1” and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”.
In pulse period measurement mode, the selected clock is counted
during the interval starting at the fall of the input signal from the
TBiIN pin to the next fall or at the rise of the input signal to the next
rise and the result is stored in the reload register. In this case, the
reload register acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input sig-
nal to the next fall. When bit 2 is “1”, the clock is counted from the
rise of the input signal to the next rise.
In the case of counting from the fall of the input signal to the next
fall, counting is performed as follows. As shown in Figure 31,
when the fall of the input signal from TBiIN pin is detected, the con-
tents of the counter is transferred to the reload register. Next the
counter is cleared and count is started from the next clock. When
the fall of the next input signal is detected, the contents of the
counter is transferred to the reload register once more, the
counter is cleared, and the count is started. The period from the
fall of the input signal to the next fall is measured in this way.
Fig. 28 Timer Bi mode register bit configuration during timer
mode
Fig. 29 Timer Bi mode register bit configuration during event
counter mode
Fig. 30 Timer Bi mode register bit configuration during pulse
period measurement/pulse width measurement mode
! : Not used in timer mode
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 0 : Select f64
1 1 : Select f512
Timer B0 mode register
5B16
Timer B1 mode register
5C16
Timer B2 mode register
5D16
Addresses
0 0 : Always “00” in timer mode
! ! : Not used in timer mode and
may be any
7654 32 1 0
0
!
0 1 : Always “01” in event counter
mode
0 0 : Count at the falling edge of input
signal
0 1 : Count at the rising edge of input
signal
1 0 : Count at the both falling edge and
rising edge of input signal
765 43 2
1
0
!!
!
1
Timer B0 mode register
5B16
Timer B1 mode register
5C16
Timer B2 mode register
5D16
Addresses
! ! ! : Not used in event counter mode
76
54
321
0
1
1 0 : Always “10” in pulse period
measurement/pulse width
measurement mode
0 0 : Count from the falling edge of
input signal to the next falling one
0 1 : Count from the rising edge of
input signal to the next rising one
1 0 : Count from the falling edge of input
signal to the next rising one
and from the rising edge to the
next falling one
Timer Bi overflow flag
Clock source selection bit
0 0 : Select f2
0 1 : Select f16
1 1 : Select f512
1 0 : Select f64
Timer B0 mode register 5B 16
Timer B2 mode register 5D16
Timer B1 mode register 5C16
Addresses
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