- 您现在的位置：买卖IC网 > PDF目录69012 > M37150EFFP 8-BIT, OTPROM, 8.95 MHz, MICROCONTROLLER, PDSO42 PDF资料下载
参数资料
| 型号： | M37150EFFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8.95 MHz, MICROCONTROLLER, PDSO42 |
| 封装： | 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件页数： | 30/62页 |
| 文件大小： | 880K |
| 代理商： | M37150EFFP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页当前第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页
33
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
____
If RTSi output is selected by setting the bit 2 of UARTi transmit/re-
____
ceive control register 0 to “1”, the RTSi output is “H” when the REi
____
flag is “0”. When the REi flag changes to “1”, the RTSi output goes
“L” to indicate receive ready and returns to “H” once receive has
____
started. In other words, RTSi output can be used to determine ex-
ternally whether the receive register is ready to receive.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 35. At this
point, the contents of the receive register is transferred to the re-
ceive buffer register and the bit 3 of UARTi transmit/receive control
register 1 is set. In other words, the RIi flag indicates that the re-
____
ceive buffer register contains data when it is set. If RTSi output is
____
selected, RTSi output goes “L” to indicate that the register is ready
to receive the next data.
The interrupt request bit in the UARTi receive interrupt control reg-
ister is set when the RIi flag changes from “0” to “1”.
The bit 4 (OERi flag) of UARTi transmission control register 1 is
set when the next data is transferred from the receive register to
the receive buffer register while the RIi flag is “1”. In other words
when an overrun error occurs. If the OERi flag is “1”, it indicates
that the next data has been transferred to the receive buffer regis-
ter before the contents of the receive buffer register has been
read.
Bit 5 (FERi flag) is set when the number of stop bits is less than
required (framing error).
Bit 6 (PERi flag) is set when a parity error occurs.
Bit 7 (SUMi flag) is set when either the OERi flag, FERi flag, or the
PERi flag is set. Therefore, the SUMi flag can be used to deter-
mine whether there is an error.
The setting of the RIi flag, OERi flag, FERi flag, and the PERi flag
is performed while transferring the contents of the receive register
to the receive buffer register. The RIi OERi, FERi, PERi, and SUMi
flags are cleared when the low order byte of the receive buffer reg-
ister is read or when the REi flag is cleared.
Sleep mode
The sleep mode is used to communicate only between certain mi-
crocomputers when multiple microcomputers are connected
through serial I/O.
The sleep mode is entered when the bit 7 of UARTi transmit/re-
ceive mode register is set.
The operation of the sleep mode for an 8-bit asynchronous com-
munication is described below.
When sleep mode is selected, the contents of the receive register
is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit
asynchronous communication and bit 8 if 9-bit asychronous com-
munication) of the received data is “0”. Also the RIi, OERi, FERi,
PERi, and the SUMi flag are unchanged. Therefore, the interrupt
request bit of the UARTi receive interrupt control register is also
unchanged.
Normal receive operation takes place when bit 7 of the received
data is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data with bit 7 set to “1” and
bits 0 to 6 set to the address of the subordinate microcomputer
which wants to communicate with. Then all subordinate microcom-
puters receive the same data. Each subordinate microcomputer
checks the received data, clears the sleep bit if bits 0 to 6 are its
own address and sets the sleep bit if not. Next the main micro-
computer sends data with bit 7 cleared. Then the microcomputer
with the sleep bit cleared will receive the data, but the microcom-
puter with the sleep bit set will not. In this way, the main
microcomputer is able to communicate with only the designated
microcomputer.
相关PDF资料 |
PDF描述 |
|---|---|
| M37151M6-XXXFP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
| M37151MC-XXXFP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
| M37151M8-XXXFP | 8-BIT, MROM, 8.1 MHz, MICROCONTROLLER, PDSO42 |
| M37207EF-XXXSP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP64 |
| M37207EF-XXXFP | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PQFP80 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M37150M6 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150M6-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150M8 | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150M8-XXXFP | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37150MA | 制造商:RENESAS 制造商全称:Renesas Technology Corp 功能描述:SNGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
发布紧急采购，3分钟左右您将得到回复。