- 您现在的位置：买卖IC网 > PDF目录132990 > M38027M8DXXXFP 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 PDF资料下载
参数资料
| 型号： | M38027M8DXXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件页数： | 9/54页 |
| 文件大小： | 590K |
| 代理商： | M38027M8DXXXFP |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页
MITSUBISHI MICROCOMPUTERS
3802 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
14
INTERRUPTS
Interrupts occur by sixteen sources: seven external, eight internal,
and one software.
Interrupt control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the corre-
sponding interrupt request and enable bits are “1” and the inter-
rupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit. The I
(interrupt disable) flag disables all interrupts except the BRK in-
struction interrupt.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering.The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on use
When the active edge of an external interrupt (INT0 to INT4,
CNTR0, or CNTR1) is changed, the corresponding interrupt re-
quest bit may also be set. Therefore, please take following se-
quence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge selection.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
Interrupt Source
Reset (Note 2)
INT0
INT1
Serial I/O1
reception
Serial I/O1
transmission
Timer X
Timer Y
Timer 1
Timer 2
CNTR0
CNTR1
Serial I/O2
INT2
INT3
INT4
A-D converter
BRK instruction
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Table 1. Interrupt vector addresses and priority
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Interrupt Request
Generating Conditions
At reset
At detection of either rising or
falling edge of INT0 input
At detection of either rising or
falling edge of INT1 input
At completion of serial I/O1
data reception
At completion of serial I/O1
transfer shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or
falling edge of CNTR0 input
At detection of either rising or
falling edge of CNTR1 input
At completion of serial I/O2
data transfer
At detection of either rising or
falling edge of INT2 input
At detection of either rising or
falling edge of INT3 input
At detection of either rising or
falling edge of INT4 input
At completion of A-D conversion
At BRK instruction execution
Remarks
Non-maskable
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O2 is selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Non-maskable software interrupt
Note 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Vector Addresses (Note 1)
相关PDF资料 |
PDF描述 |
|---|---|
| MB90549GPMC | 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100 |
| MB90347CESPMC | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100 |
| MB90348ESPMC | 16-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP100 |
| MB90F343ESPMC | 16-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP100 |
| MB90F423GCPMC | 16-BIT, FLASH, 16 MHz, MICROCONTROLLER, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M3802-BLACK-100 | 制造商:Alpha Wire 功能描述: |
| M3803 BK005 | 制造商:Alpha Wire 功能描述:CBL 5COND 18AWG BLK 100' |
| M38037M5H-175HP#U0 | 制造商:Renesas Electronics Corporation 功能描述:8BIT CISC - Trays |
| M38037M8108F | 制造商:Panasonic Industrial Company 功能描述:IC |
| M38037M8H-194HP#U0 | 制造商:Renesas Electronics Corporation 功能描述:8BIT CISC - Trays |
发布紧急采购，3分钟左右您将得到回复。