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| 型号： | M38030F8L-XXXHP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 38/119页 |
| 文件大小： | 1575K |
| 代理商： | M38030F8L-XXXHP |
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Rev.1.00
Apr 2, 2007
Page 25 of 117
REJ03B0212-0100
3803 Group (Spec.L)
INTERRUPTS
The 3803 group (Spec.L) interrupts are vector interrupts with a
fixed priority scheme, and generated by 16 sources among 21
sources: 8 external, 12 internal, and 1 software.
The interrupt sources, vector addresses(1), and interrupt priority
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 20 shows an interrupt control diagram.
An interrupt requests is accepted when all of the following
conditions are satisfied:
Interrupt disable flag.................................“0”
Interrupt request bit...................................“1”
Interrupt enable bit....................................“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Table 8
Interrupt vector addresses and priority
Interrupt Source
Priority
Vector
Addresses(1)
Interrupt Request Generating
Conditions
Remarks
High
Low
Reset(2)
1FFFD16
FFFC16
At reset
Non-maskable
INT0
2FFFB16
FFFA16
At detection of either rising or falling
edge of INT0 input
External interrupt
(active edge selectable)
Timer Z
At timer Z underflow
INT1
3
FFF916
FFF816
At detection of either rising or falling
edge of INT1 input
External interrupt
(active edge selectable)
Serial I/O1 reception
4
FFF716
FFF616
At completion of serial I/O1 data
reception
Valid when serial I/O1 is selected
Serial I/O1
transmission
5
FFF516
FFF416
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
Valid when serial I/O1 is selected
Timer X
6
FFF316
FFF216
At timer X underflow
Timer Y
7
FFF116
FFF016
At timer Y underflow
Timer 1
8
FFEF16
FFEE16
At timer 1 underflow
STP release timer underflow
Timer 2
9
FFED16
FFEC16
At timer 2 underflow
CNTR0
10
FFEB16
FFEA16
At detection of either rising or falling
edge of CNTR0 input
External interrupt
(active edge selectable)
CNTR1
11
FFE916
FFE816
At detection of either rising or falling
edge of CNTR1 input
External interrupt
(active edge selectable)
Serial I/O3 reception
At completion of serial I/O3 data
reception
Valid when serial I/O3 is selected
Serial I/O2
12
FFE716
FFE616
At completion of serial I/O2 data
transmission or reception
Valid when serial I/O2 is selected
Timer Z
At timer Z underflow
INT2
13
FFE516
FFE416
At detection of either rising or falling
edge of INT2 input
External interrupt
(active edge selectable)
INT3
14
FFE316
FFE216
At detection of either rising or falling
edge of INT3 input
External interrupt
(active edge selectable)
INT4
15
FFE116
FFE016
At detection of either rising or falling
edge of INT4 input
External interrupt
(active edge selectable)
CNTR2
At detection of either rising or falling
edge of CNTR2 input
External interrupt
(active edge selectable)
A/D conversion
16
FFDF16
FFDE16
At completion of A/D conversion
Serial I/O3
transmission
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
Valid when serial I/O3 is selected
BRK instruction
17
FFDD16
FFDC16
At BRK instruction execution
Non-maskable software interrupt
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