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| 型号： | M38030F8L-XXXHP |
| 厂商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 单芯片8位CMOS微机 |
| 文件页数： | 51/119页 |
| 文件大小： | 1575K |
| 代理商： | M38030F8L-XXXHP |
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Rev.1.00
Apr 2, 2007
Page 37 of 117
REJ03B0212-0100
3803 Group (Spec.L)
(6) Programmable waveform generating mode
Mode selection
This mode can be selected by setting “100” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
In low-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64, 1/128, 1/256,
1/512 or 1/1024 of f(XCIN); or f(XCIN) can be selected as the
count source.
Interrupt
The interrupt at an underflow is the same as the timer mode’s.
Explanation of operation
The operation is the same as the timer mode’s. Moreover the
timer outputs the data set in the output level latch (bit 4) of the
timer Z mode register (address 002A16) from the CNTR2 pin
each time the timer underflows.
Changing the value of the output level latch and the timer latch
after an underflow makes it possible to output an optional
waveform from the CNTR2 pin.
Precautions
The double-function port of CNTR2 pin and port P47 is
automatically set to the programmable waveform generating port
in this mode.
Figure 34 shows the timing chart of the programmable waveform
generating mode.
(7) Programmable one-shot generating mode
Mode selection
This mode can be selected by setting “101” to the timer Z
operating mode bits (bits 2 to 0) and setting “0” to the
timer/event counter mode switch bit (b7) of the timer Z mode
register (address 002A16).
Count source selection
In high- or middle-speed mode, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64,
1/128, 1/256, 1/512 or 1/1024 of f(XIN); or f(XCIN) can be
selected as the count source.
Interrupt
The interrupt at an underflow is the same as the timer mode’s.
The trigger to generate one-shot pulse can be selected by the INT1
active edge selection bit (bit 1) of the interrupt edge selection
register (address 003A16). When it is “0”, the falling edge active is
selected; when it is “1”, the rising edge active is selected.
When the valid edge of the INT1 pin is detected, the INT1
interrupt request bit (bit 1) of the interrupt request register 1
(address 003C16) is set to “1”.
Explanation of operation
1. “H” one-shot pulse; Bit 5 of timer Z mode register = “0”
The output level of the CNTR2 pin is initialized to “L” at
mode selection. When trigger generation (input signal to
INT1 pin) is detected, “H” is output from the CNTR2 pin.
When an underflow occurs, “L” is output. The “H” one-shot
pulse width is set by the setting value to the timer Z register
low-order and high-order. When trigger generating is
detected during timer count stop, although “H” is output
from the CNTR2 pin, “H” output state continues because an
underflow does not occur.
2. “L” one-shot pulse; Bit 5 of timer Z mode register = “1”
The output level of the CNTR2 pin is initialized to “H” at
mode selection. When trigger generation (input signal to
INT1 pin) is detected, “L” is output from the CNTR2 pin.
When an underflow occurs, “H” is output. The “L” one-shot
pulse width is set by the setting value to the timer Z low-
order and high-order. When trigger generating is detected
during timer count stop, although “L” is output from the
CNTR2 pin, “L” output state continues because an under-
flow does not occur.
Precautions
Set the double-function port of INT1 pin and port P42 to input in
this mode.
The double-function port of CNTR2 pin and port P47 is
automatically set to the programmable one-shot generating port
in this mode.
This mode cannot be used in low-speed mode.
If the value of the CNTR2 active edge switch bit is changed
during one-shot generating enabled or generating one-shot pulse,
then the output level from CNTR2 pin changes.
Figure 35 shows the timing chart of the programmable one-shot
generating mode.
<Notes regarding all modes>
Timer Z write control
Which write control can be selected by the timer Z write control
bit (bit 3) of the timer Z mode register (address 002A16), writing
data to both the latch and the timer at the same time or writing
data only to the latch.
When the operation “writing data only to the latch” is selected,
the value is set to the timer latch by writing data to the address of
timer Z and the timer is updated at next underflow. After reset
release, the operation “writing data to both the latch and the timer
at the same time” is selected, and the value is set to both the latch
and the timer at the same time by writing data to the address of
timer Z.
In the case of writing data only to the latch, if writing data to the
latch and an underflow are performed almost at the same time,
the timer value may become undefined.
Timer Z read control
A read-out of timer value is impossible in pulse period
measurement mode and pulse width measurement mode. In the
other modes, a read-out of timer value is possible regardless of
count operating or stopped.
However, a read-out of timer latch value is impossible.
Switch of interrupt active edge of CNTR2 and INT1
Each interrupt active edge depends on setting of the CNTR2
active edge switch bit and the INT1 active edge selection bit.
Switch of count source
When switching the count source by the timer Z count source
se lec tion bi ts, t h e va lue of t imer count is al tered in
inconsiderable amount owing to generating of thin pulses on the
count input signals.
Therefore, select the timer count source before setting the value
to the prescaler and the timer.
Usage of CNTR2 pin as normal I/O port P47
To use the CNTR2 pin as normal I/O port P47, set timer Z
operating mode bits (b2, b1, b0) of timer Z mode register
(address 002A16) to “000”.
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