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95
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Read-only Mode
The microcomputer enters the read-only mode by applying VPPL
to the VPP pin. In this mode, the user can input the address of a
memory location to be read and the control signals at the timing
shown in Figure 88, and the M38039FF/M38049FF will output the
contents of the user’s specified address from data I/O pin to the
external. In this mode, the user cannot perform any operation
other than read.
Fig. 88 Read timing
Read/Write Mode
The microcomputer enters the read/write mode by applying VPPH
to the VPP pin. In this mode, the user must first input a software
command to choose the operation (e. g., read, program, or erase)
to be performed on the flash memory (this is called the first cycle),
and then input the information necessary for execution of the com-
mand (e.g, address and data) and control signals (this is called
the second cycle). When this is done, the M38039FF/M38049FF
executes the specified operation.
Table 19 shows the software commands and the input/output in-
formation in the first and the second cycles. The input address is
___
latched internally at the falling edge of the WE input; software
commands and other input data are latched internally at the rising
___
edge of the WE input.
The following explains each software command. Refer to Figures 89
to 91 for details about the signal input/output timings.
Table 19 Software command (Parallel input/output mode)
Symbol
Read
Program
Program verify
Erase
Erase verify
Reset
Device identification
Address input
×
Verify address
×
First cycle
Data input
0016
4016
C016
2016
A016
FF16
9016
Address input
Read address
Program address
×
ADI
Second cycle
Data I/O
Read data (Output)
Program data (Input)
Verify data (Output)
2016 (Input)
Verify data (Output)
FF16 (Input)
DDI (Output)
Note: ADI = Device identification address : manufacturer’s code 0000016, device code 0000116
DDI = Device identification data : manufacturer’s code 1C16, device code D016
X can be VIL or VIH.
Address
Valid address
tRC
ta(CE)
tWRR
tDF
ta(OE)
tDH
tOLZ
Floating
tCLZ
ta(AD)
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CE
OE
WE
Data
Dout