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参数资料
| 型号： | M38039MC-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 16.8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, QFP-64 |
| 文件页数： | 41/136页 |
| 文件大小： | 2007K |
| 代理商： | M38039MC-XXXFP |
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REVISION HISTORY
3803/3804 GROUP DATA SHEET
Rev.
Date
Description
Page
Summary
(4/5)
3.0
06/28/00
124
125
Limits and unit of tw(RESET) into Table 36 are revised.
Limits of tWH(SCLK1), tWH(SCLK3) into Tables 37 and 38 are partly added.
4.0
05/15/02
9
15
21
22
23
24
25
26
31
42
43
44
54
55
56
62
63
70
71
76
77
78
83
87
89
91
93
94
95
96
97
98
Figure 8 is partly revised.
Sub-sub clause name of “qMiddle-speed mode automatic switch by program” is
partly eliminated.
Figure 16 is partly revised.
Figure 17 is partly revised.
Figure 18 is partly revised.
Figure 19 is partly revised.
Figure 20 is partly revised.
Figure 21 is partly revised.
Explanations of “sNotes” are revised.
Explanations of “q16-bit Timers” are partly revised.
Explanations of “qExplanation of operation” of “(4) Pulse period measurement
mode” are revised.
Explanations of “qExplanation of operation” of “(5) Pulse width measurement mode”
are revised.
Explanations of “qExplanation of operation” of “(7) Programmable one-shot gen-
erating mode” are partly revised.
Explanations of “qNote” of “2.1 Stop of transmission operation” are partly added.
Explanations of “qNote 1 (only transmission operation is stopped)” of “2.3 Stop of
transmit/receive operation” are partly added.
Explanations of “5. Data transmission control with referring to transmit shift regis-
ter completion flag” are partly added.
Figure 46 is partly revised.
Explanations of “qNote” of “2.1 Stop of transmission operation” are partly added.
Explanations of “qNote 1 (only transmission operation is stopped)” of “2.2 Stop of
transmit/receive operation” are partly added.
Explanations of “5. Data transmission control with referring to transmit shift regis-
ter completion flag” are partly added.
Explanations of “MULTI-MASTER I2C-BUS INTERFACE” are partly revised.
Explanations of “[I2C Data Shift Register (S0)]” are partly revised.
Explanations of “START Condition Generating Method” are partly revised.
Table 14 is partly revised.
Table 15 is partly revised.
Explanations of “2” of “(2) Start condition generating procedure using multi-mas-
ter” are partly revised.
Explanations of “CLOCK GENERATING CIRCUIT” are partly revised.
Explanations of “sNote” of “(2) Wait mode” are partly added.
Figure 84 is partly revised.
Explanations of “(1) Flash memory mode 1 (parallel I/O mode)” are partly revised.
Table 16 is partly revised.
Figure 86 is partly revised.
Figure 87 is partly revised.
Explanations of “Read-only Mode” are partly revised.
Explanations of “Read/Write Mode” are partly revised.
Explanations of “qRead command” are partly revised.
Explanations of “qProgram command” are partly revised.
Explanations of “qProgram verify command” are partly revised.
Explanations of “qErase verify command” are partly revised.
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