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参数资料
| 型号： | M38073E4FS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CQCC80 |
| 封装： | 0.80 MM PITCH, CERAMIC, LCC-80 |
| 文件页数： | 37/77页 |
| 文件大小： | 1126K |
| 代理商： | M38073E4FS |
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39
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
[Transmit Buffer Register/Receive Buffer Register] TB/RB (001816)
The transmit buffer and the receive buffer are located in the same
address. The transmit buffer is write-only and the receive buffer is
read-only. If a character bit length is 7 bits, the MSB of data stored in
the receive buffer is "0".
[Serial I/O 1 Status Register] SIO1STS (001916)
The read-only serial I/O1 status register consists of seven flags (b0
to b6) which indicate the operating status of the serial I/O1 function
and various errors. Three of the flags (b4 to b6) are only valid in
UART mode. The receive buffer full flag (b1) is cleared to "0" when
the receive buffer is read.
The error detection is performed at the same time data is transferred
from the receive shift register to the receive buffer register, and the
receive buffer full flag is set. A writing to the serial I/O1 status regis-
ter clears all the error flags OE, PE, FE, and SE (b3 to b6, respec-
tively). Writing "0" to the serial I/O1 enable bit (SIOE : b7 of the serial
I/O1 control register) also clears all the status flags, including the
error flags.
All bits of the serial I/O1 status register are initialized to "0" at reset,
but if the transmit enable bit (b4) of the serial I/O1 control register
has been set to "1", the transmit shift register shift completion flag
(b2) and the transmit buffer empty flag (b0) become "1."
[Serial I/O1 Control Register] SIO1CON (001A16)
The serial I/O1 control register contains eight control bits for serial
I/O1 functions.
[UART Control Register] UARTCON (001B16)
The UART control register consists of four control bits (b0 to b3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer. One bit in this register (b4) is
always valid and sets the output structure of the P45/TxD pin.
[Baud Rate Generator] BRG (001C16)
The baud rate generator determines the baud rate for serial transfer.
With the 8-bit counter having a reload register the baud rate genera-
tor divides the frequency of the count source by 1/(n+1), where n is
the value written to the baud rate generator.
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift register shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns "1" when read)
Serial I/O1 status register
(SIO1STS : address 001916)
Serial I/O1 control register
(SIO1CON : address 001A16)
b0
BRG count source selection bit (CSS)
0: f(XIN)
(f(XCIN) in low-peed mode)
1: f(XIN)/4
((XCIN)/4 in low-speed mode)
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG/ 4
(when clock synchronous serial I/O is selected)
BRG/16 (UART is selected)
1: External clock input
(when clock synchronous serial I/O is selected)
External clock input/16 (UART is selected)
SRDY1 output enable bit (SRDY)
0: P47 pin operates as ordinaly I/O pin
1: P47 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Asynchronous serial I/O (UART)
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P44 to P47 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P44 to P47 operate as serial I/O pins)
b7
UART control register
(UARTCON : address 001B16)
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity cheching disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P45/TXD P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode)
Not used (return "1" when read)
b0
Fig. 37. Structure of serial I/O1 related register
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