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参数资料
| 型号： | M38073E4FS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, UVPROM, 4 MHz, MICROCONTROLLER, CQCC80 |
| 封装： | 0.80 MM PITCH, CERAMIC, LCC-80 |
| 文件页数： | 46/77页 |
| 文件大小： | 1126K |
| 代理商： | M38073E4FS |
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47
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
Port P2P3 control register
(P2P3C : address 001516)
b7
P34 clock output control bit
0: I/O port
1: Clock output
Output clock frequency selection bits
000:
φ
001: f(XCIN)
010: "L" fixed for output
011: "L" fixed for output
100: f(XIN)
(f(XCIN) in low-speed mode)
101: f(XIN)/2 (f(XCIN)/2 in low-speed mode)
110: f(XIN)/4 (f(XCIN)/4 in low-speed mode)
111: f(XIN)/16 (f(XCIN)/16 in low-speed mode)
Not used (return "0" when read)
P2P32 input level selection bit
0: CMOS level input
1: TTL level input
Clock output function
The internal clock
φ can be output from I/O port P34. Control of I/O
ports and clock output function can be performed by port P2P3
control register (address 001516).
(1) I/O ports or clock output function selection
The P34 clock output control bit (b0) of port P2P3 control register
selects the I/O port or clock output function. When clock output
function is selected, the clock is output regardless of the port P34
direction register settings.
Directly after bit 0 is written to, the port or clock output is switched
synchronous to a falling edge of clock frequency selected by the
output clock frequency selection bit. When memory expansion mode
or microprocessor mode is selected in CPU mode register (b1, b0),
clock output is selected on regardless of P34 clock output control bit
settings or port P34 direction register settings.
(2) Selection of output clock frequency
The output clock frequency selection bits (b3, b2, b1) of port P2P3
control register select the output clock frequency.
The output waveform when f(XIN) or f(XCIN) is selected, depends on
XIN or XCIN input waveform however; all other output waveform
settings have a duty cycle of 50%.
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
P34 port latch
P34/CKOUT/
1/2
"110"
"100"
Output clock frequency
selection bits
XIN
1/4
"101"
"111"
1/16
"000"
XCIN
"001"
Main clock division ratio
selection bits (Note)
Low-speed mode
P34 direction register
P34 clock output control bit
Microprocessor mode/memory expansion mode
"010"
"011"
High-speed or
middle-speed
mode
Fig. 51. Block diagram of Clock output function
Fig. 50. Structure of Port P2P3 control register
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