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参数资料
| 型号： | M38513M4-XXXFP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO42 |
| 封装： | 0.450 INCH, PLASTIC, SSOP-42 |
| 文件页数： | 24/91页 |
| 文件大小： | 1295K |
| 代理商： | M38513M4-XXXFP |
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30
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3851 Group
(Built-in 24 KB or more ROM)
[I2C Data Shift Register (S0)] 002B16
The I2C data shift register (S0 : address 002B16) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to
the outside from bit 7 in synchronization with the SCL clock, and
each time one-bit data is output, the data of this register are
shifted by one bit to the left. When data is received, it is input to
this register from bit 0 in synchronization with the SCL clock, and
each time one-bit data is input, the data of this register are shifted
by one bit to the left. The minimum 2 machine cycles are required
from the rising of the SCL clock until input to this register.
The I2C data shift register is in a write enable status only when the
I2C-BUS interface enable bit (ES0 bit : bit 3 of address 002E16) of
the I2C control register is “1”. The bit counter is reset by a write in-
struction to the I2C data shift register. When both the ES0 bit and
the MST bit of the I2C status register (address 002D16) are “1,” the
SCL is output by a write instruction to the I2C data shift register.
Reading data from the I2C data shift register is always enabled re-
gardless of the ES0 bit value.
[I2C Address Register (S0D)] 002C16
The I2C address register (address 002C16) consists of a 7-bit
slave address and a read/write bit. In the addressing mode, the
slave address written in this register is compared with the address
data to be received immediately after the START condition is de-
tected.
Bit 0: Read/write bit (RWB)
This is not used in the 7-bit addressing mode. In the 10-bit ad-
dressing mode, the first address data to be received is compared
with the contents (SAD6 to SAD0 + RWB) of the I2C address reg-
ister.
The RWB bit is cleared to “0” automatically when the stop condi-
tion is detected.
Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data
transmitted from the master is compared with the contents of
these bits.
Fig. 28 Structure of I2C address register
SAD6 SAD5 SAD4SAD3SAD2 SAD1 SAD0 RWB
Slave address
I2C address register
(S0D: address 002C16)
Read/write bit
b7
b0
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