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参数资料
型号： M38K29F8LHP
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封装： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件页数： 22/126页
文件大小： 2167K
代理商： M38K29F8LHP
1-99
38K2 Group User’s Manual
HARDWARE
FUNCTIONAL DESCRIPTION
Notes
Reset
C
M
7
“1
”←
→
“0
”
CM6
“0”
←→“1”
XIN 8-divide mode
f(
φ) = 0.75 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = 00
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly
without an allow.)
2 : Set the USB clock (fUSB) to 48 MHz when switching the system clock to fSYN.
3 : Do not change a division ratio of USB clock when using fSYN as the system clock.
4 : See section “PLL CIRCUIT” in details for enabling/disabling PLL operation and usage notes of fSYN.
5 : Set the system clock to XIN when entering STOP mode.
6 : In all modes, switching to WAIT mode is possible. When it is released, the MCU returns to the original mode. In
WAIT mode the timers can operate.
C
M
5
“1
”←
→
“0
”
Remarks : This diagram assumes that the 6 MHz signals are applied to XIN pin.
XIN 4-divide mode
f(
φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
C
M
7
“1
”←
→
“0
”
C
M
6
“0
”
←
→
“1
”
C
M
7
“0
”
←
→
“1
”
C
M
6
“0
”←
→
“1
”
C
M
7
“1
”←
→
“0
”
XIN 2-divide mode
f(
φ) = 3.0 MHz
CM7 = 1
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
CM6
“0”
←→“1”
XIN through mode
f(
φ) = 1.5 MHz
CM7 = 0
CM6 = 0
CM5 = 0
PLLCON [4:3] = xx
(arbitrary)
f(SYN) 2-divide mode
f(
φ) = 6.0 MHz
CM7 = 1
CM6 = 0
CM5 = 1
PLLCON [4:3] = 10
f(SYN) through mode
f(
φ) = 6.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 00
f(SYN) through mode
f(
φ) = 8.0 MHz
CM7 = 1
CM6 = 1
CM5 = 1
PLLCON [4:3] = 01
Note:
Set PLLCON [4:3] = 10 before
switching the system clock from XIN
to fSYN.
CM5
“0”
←→“1”
CM6
“0”
←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
CM5
“0”
←→“1”
CM6
“0”
←→“1”
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
CM5
“0”
←→“1”
CM5
“0”
←→“1”
Note:
Set PLLCON [4:3] = 00 before switching
the system clock from XIN to fSYN.
Note:
Set PLLCON [4:3] = 01 before switching
the system clock from XIN to fSYN.
Fig. 145 State transitions of clock
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相关代理商/技术参数
参数描述
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M38K29F8LHP#UO 制造商:Renesas Electronics Corporation 功能描述:
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