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| 型号： | M38K29F8LHP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封装： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件页数： | 6/126页 |
| 文件大小： | 2167K |
| 代理商： | M38K29F8LHP |
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HARDWARE
1-84
38K2 Group User’s Manual
FUNCTIONAL DESCRIPTION
(3) Memory Channel Receiving Operation (1)-
Cycle Mode
Memory channel receiving operation (1) is shown bellow.
Fig. 124 Memory channel receiving operation (1)
DMA acknowledge
ExDACK
#0
#1
Mch_req
mWR
detection
mWR
detection
#0
#1
012
3
5
req
010016
010116
010216
ack
DMA request
ExDREQ
’
Address ExA0
Chip select ExCS
Read ExRD
Write ExWR
Data DQ0 to DQ7
Internal clock
φ
Receive buffer RXBUF
Operation enabled
Main sequencer
Internal memory access
Acknowledgment of
internal memory access
Memory address
Counter end
Memory channel operation
end interrupt
A0 = “0”
CS = “0”
A0 = “0”
CS = “0”
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register
MC_DIR[1:0] (Memory channel direction control) = 012 (Receive mode)
Burst (burst) = “0” (Cycle mode)
Memory address counter
(Example) 010016
End address register
(Example) 010116
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
In the memory channel receive mode when the command for enabling operation is written, operation starts (main sequencer starts) and assertion of the
memory channel request which synchronized with a rise of
φ is made.
When the external MCU bus is in the condition of ExCS = “L” and ExA0 = “L” or a fall of ExWR is detected in the condition of ExDACK = “L”, negation of the
memory channel request which synchronized with a rise of
φ is made.
When a rise of ExWR is detected, an internal memory access sequence which synchronized with a rise of φ is activated and a data is written in the internal
memory within two clocks at a minimum.
The memory address counter is increased simultaneously at write completion and assertion of the next memory channel request is made.
When the write operation to the end address has been completed, the memory address counter is increased, but assertion of the next memory channel
request is not made and the memory channel operation end interrupt is generated.
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相关代理商/技术参数 |
参数描述 |
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| M38K29T-PAC | 制造商:Renesas Electronics Corporation 功能描述:DEV SIMPLE TOOL SYSTEM PKG FOR 38000/38K - Bulk |
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