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参数资料
| 型号： | M4-64/32-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 11/46页 |
| 文件大小： | 754K |
| 代理商： | M4-64/32-15JC |
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MACH 4 Family
19
MACH 4 TIMING MODEL
The primary focus of the MACH 4 timing model is to accurately represent the timing in a MACH
4 device, and at the same time, be easy to understand. This model accurately describes all
combinatorial and registered paths through the device, making a distinction between internal
feedback and external feedback. A signal uses internal feedback when it is fed back into the
switch matrix or block without having to go through the output buffer. The input register
specications are also reported as internal feedback. When a signal is fed back into the switch
matrix after having gone through the output buffer, it is using external feedback.
The parameter, tBUF, is dened as the time it takes to go from feedback through the output buffer
to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter
designator is followed by an “i”. By adding tBUF to this internal parameter, the external parameter
is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized MACH 4
timing model is shown in Figure 15. Refer to the Technical Note entitled MACH 4 Timing and
High Speed Design for a more detailed discussion about the timing parameters.
SPEEDLOCKING FOR GUARANTEED FIXED TIMING
The MACH 4 architecture allows allocation of up to 20 product terms to an individual macrocell
with the assistance of an XOR gate without incurring additional timing delays.
The design of the switch matrix and PAL blocks guarantee a xed pin-to-pin delay that is
independent of the logic required by the design. Other competitive CPLDs incur serious timing
delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and
SpeedLocking combine to give designs easy access to the performance required in today’s
designs.
(External Feedback)
(Internal Feedback)
INPUT REG/
INPUT LATCH
tSIRS
tHIRS
tSIL
tHIL
tSIRZ
tHIRZ
tSILZ
tHILZ
tPDILi
tICOSi
tIGOSi
tPDILZi
Q
tSS(T)
tSA(T)
tH(S/A)
tS(S/A)L
tH(S/A)L
tSRR
tPDi
tPDLi
tCO(S/A)i
tGO(S/A)i
tSRi
COMB/DFF/TFF/
LATCH/SR*/JK*
S/R
IN
BLK CLK
OUT
tPL
tBUF
tEA
tER
tSLW
Q
Central
Switch
Matrix
*emulated
17466G-025
Figure 15. MACH 4 Timing Model
相关PDF资料 |
PDF描述 |
|---|---|
| M4-64/32-15VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12YC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12YI | High Performance E 2 CMOS In-System Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M4644 SL001 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 1000' |
| M4644 SL002 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 500' |
| M4644 SL005 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 100' |
| M4644 SL199 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 1000=1000' |
| M4644-SL001 | 制造商:Alpha Wire 功能描述: |
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