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参数资料
| 型号： | M4-64/32-15JC |
| 厂商： | LATTICE SEMICONDUCTOR CORP |
| 元件分类： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 15 ns, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 44/46页 |
| 文件大小： | 754K |
| 代理商： | M4-64/32-15JC |
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MACH 4 Family
7
Product-Term Array
The product-term array consists of a number of product terms that form the basis of the logic
being implemented. The inputs to the AND gates come from the central switch matrix (Table 5),
and are provided in both true and complement forms for efcient logic implementation.
Logic Allocator
Within the logic allocator, product terms are allocated to macrocells in “product term clusters.”
The availability and distribution of product term clusters are automatically considered by the
software as it ts functions within a PAL block. The size of a product term cluster has been
optimized to provide high utilization of product terms, making complex functions using many
product terms possible. Yet when few product terms are used, there will be a minimal number
of unused—or wasted—product terms left over. The product term clusters available to each
Each product term cluster is associated with a macrocell. The size of a cluster depends on the
conguration of the associated macrocell. When the macrocell is used in synchronous mode
(Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in
asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term
cluster is routed to a different macrocell, the allocator conguration is not determined by the
mode of the macrocell actually being driven. The conguration is always set by the mode of the
macrocell that the cluster will drive if not routed away, regardless of the actual routing.
In addition, there is an extra product term that can either join the basic cluster to give an
extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included
with the basic cluster, this provides for up to 20 product terms on a synchronous function that
uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18
product terms.
When the extra product term is used to extend the cluster, the value of the second XOR input
can be programmed as a 0 or a 1, giving polarity control. The possible congurations of the logic
Table 5. PAL Block Inputs
Device
Number of Inputs to PAL Block
M4-32/32 and M4LV-32/32
M4-64/32 and M4LV-64/32
M4-96/48 and M4LV-96/48
M4-128/64 and M4LV-128/64
M4-128N/64 and M4LV-128N/64
33
M4-192/96 and M4LV-192/96
M4-256/128 and M4LV-256/128
34
相关PDF资料 |
PDF描述 |
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| M4-64/32-15VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12VC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12VI | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12YC | High Performance E 2 CMOS In-System Programmable Logic |
| M4LV-128/64-12YI | High Performance E 2 CMOS In-System Programmable Logic |
相关代理商/技术参数 |
参数描述 |
|---|---|
| M4644 SL001 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 1000' |
| M4644 SL002 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 500' |
| M4644 SL005 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 100' |
| M4644 SL199 | 制造商:Alpha Wire Company 功能描述:CBL 20COND 22AWG SLT 1000=1000' |
| M4644-SL001 | 制造商:Alpha Wire 功能描述: |
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