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Clock operation
M41ST87Y, M41ST87W
3
Clock operation
The eight byte clock register (see
Table 7 on page 29) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. Tenths/hundredths
of seconds, seconds, minutes, and hours are contained within the first four registers.
Note:
A WRITE to any clock register will result in the tenths/hundredths of seconds being reset to
“00,” and tenths/hundredths of seconds cannot be written to any value other than “00.”
Bits D6 and D7 of clock register 03h (century/hours register) contain the CENTURY bit 0
(CB0) and CENTURY bit 1 (CB1). Bits D0 through D2 of register 04h contain the day (day of
week). Registers 05h, 06h, and 07h contain the date (day of month), month, and years. The
ninth clock register is the control register (this is described in the clock calibration section).
Bit D7 of register 01h contains the STOP bit (ST). Setting this bit to a '1' will cause the
oscillator to stop. If the device is expected to spend a significant amount of time on the shelf,
the oscillator may be stopped to reduce current drain. When reset to a '0' the oscillator
restarts within one second (typical).
Note:
A WRITE to ANY location within the first eight bytes of the clock register (00h-07h),
including the OFIE bit, CLRPW0 bit, CLRPW1 bit, THS bit, and so forth, will result in an
update of the system clock and a reset of the divider chain. This could result in a significant
stamp) has not been previously reset. These non-clock related bits should be written prior to
setting the clock, and remain unchanged until such time as a new clock time is also written.
The eight clock registers may be read one byte at a time, or in a sequential block. The
control register (address location 08h) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the eight clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. This will prevent a transition of data during the READ.
3.0.1
Power-down time-stamp
Upon power-up following a power failure, the halt update bit (HT) will automatically be set to
a '1.' This will prevent the clock from updating the TIMEKEEPER registers, and will allow
the user to read the time of the power-down event.
Note:
When the HT bit is set or a tamper event occurs, the tenths/hundredths of a second register
(00h) will automatically be reset to a value of “00.” All other date and time registers (01h -
07h) will retain the value last updated prior to the power-down or tamper event. The internal
clock remains accurate and no time is lost as a result of the zeroing of the tenth/hundredths
of a second register. When updates are resumed (due to resetting the HT bit or TEB bit), the
correct time will be displayed.
Resetting the HT bit to a '0' will allow the clock to update the TIMEKEEPER registers with
the current time.
Note:
If the TEB bit is set, the power down time-stamp will be disabled, and the tamper event time-