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参数资料
| 型号： | M41ST87YMX6TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO28 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, SOX-28 |
| 文件页数： | 8/48页 |
| 文件大小： | 457K |
| 代理商： | M41ST87YMX6TR |
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Operating modes
M41ST87Y, M41ST87W
2.3
WRITE mode
In this mode the master transmitter transmits to the M41ST87Y/W slave receiver. Bus
protocol is shown in Figure 11. Following the START condition and slave address, a logic '0'
(R/W=0) is placed on the bus and indicates to the addressed device that word address An
will follow and is to be written to the on-chip address pointer. The data word to be written to
the memory is strobed in next and the internal address pointer is incremented to the next
memory location within the RAM on the reception of an acknowledge clock. The
M41ST87Y/W slave receiver will send an acknowledge clock to the master transmitter after
it has received the slave address (see Figure 8 on page 15) and again after it has received
the word address and each data byte.
Figure 11.
WRITE mode sequence
Figure 12.
WRITE cycle timing: RTC & external SRAM control signals
2.4
Data retention mode
With valid VCC applied, the M41ST87Y/W can be accessed as described above with READ
or WRITE Cycles. Should the supply voltage decay, the M41ST87Y/W will automatically
deselect, write protecting itself (and any external SRAM) when VCC falls between VPFD
accomplished by internally inhibiting access to the clock registers. At this time, the Reset pin
(RST) is driven active and will remain active until VCC returns to nominal levels. External
RAM access is inhibited in a similar manner by forcing ECON to a high level. This level is
within 0.2 volts of the VBAT. ECON will remain at this level as long as VCC remains at an out-
of-tolerance condition. When VCC falls below the battery backup switchover voltage (VSO),
AI00591
BUS ACTIVITY:
ACK
S
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
AI03663
EX
ECON
tEXPD
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相关代理商/技术参数 |
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| M41ST87YSS6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM |
| M41ST87YSS6F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 V and 3.3/3.0 V secure serial RTC and NVRAM supervisor with tamper detection and 128 bytes of clearable NVRAM |
| M41ST95W | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
| M41ST95WMH6E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:5.0 or 3.0V, 512 bit (64 bit X 8) Serial RTC (SPI) SRAM and NVRAM Supervisor |
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