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参数资料
| 型号： | M44C892 |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SSO-20 |
| 文件页数： | 10/84页 |
| 文件大小： | 643K |
| 代理商： | M44C892 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
18 (84)
4–MHz
oscillator
4Out
13761
OSC1
OSC2
*
Oscin
C1
*
C2
Oscout
XTAL
4 MHz
*
mask option
Stop
Osc–Stop
Figure 18. 4-MHz crystal oscillator
4–MHz
oscillator
4Out
Stop
4Out
Osc–Stop
13762
OSC1
OSC2
*
Oscin
C1
*
C2
Oscout
Cer.
Res
*
mask option
C3
C4
Figure 19. Ceramic resonator
32-kHz Oscillator
Some applications require long-term time keeping or low
resolution timing. In this case, an on–chip, low power
32-kHz crystal oscillator can be used to generate both the
SUBCL
and
the SYSCL. In this mode, power
consumption is greatly reduced. The 32-kHz crystal
oscillator can not be stopped while the power-down mode
is in operation.
32–kHz
oscillator
32Out
13763
OSC1
OSC2
*
Oscin
C1
*
C2
Oscout
XTAL
32 kHz
*
mask option
Figure 20. 32-kHz crystal oscillator
2.5.3
Clock Management
The clock management register controls the system clock
divider and synchronization stage. Writing to this register
triggers the synchronization cycle.
Clock Management Register (CM)
Auxiliary register address: ’3’hex
Bit 3
Bit 2
Bit 1
Bit 0
CM:
NSTOP
CCS
CSS1
CSS0
Reset value: 1111b
NSTOP
Not STOP peripheral clock
NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
CCS
Core Clock Select
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on
the setting of OS0 and OS1 in the system configuration register
CSS1
Core Speed Select 1
CSS0
Core Speed Select 0
CSS1
CSS0
Divider
Note
0
0
16
1
1
8
Reset value
1
0
4
0
1
2
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