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参数资料
| 型号： | M44C892 |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SSO-20 |
| 文件页数： | 2/84页 |
| 文件大小： | 643K |
| 代理商： | M44C892 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
10 (84)
2.2.4
ALU
TOS–1
CCR
RAM
TOS–2
SP
TOS–3
TOS
ALU
TOS–4
94 8977
Figure 7. ALU zero-address operations
The 4-bit ALU performs all the arithmetic, logical, shift
and rotate operations with the top two elements of the
expression stack (TOS and TOS–1) and returns the result
to the TOS. The ALU operations affect the carry/borrow
and branch flag in the condition code register (CCR).
2.2.5
I/O Bus
The I/O ports and the registers of the peripheral modules
are I/O mapped. All communication between the core and
the on-chip peripherals takes place via the I/O bus and the
associated I/O control. With the MARC4 IN and OUT
instructions the I/O bus allows a direct read or write
access to one of the 16 primary I/O addresses. More about
the I/O access to the on-chip peripherals is described in
the section ”Peripheral Modules”. The I/O bus is internal
and is not accessible by the customer on the final micro-
controller device, but it is used as the interface for the
MARC4 emulation (see also the section ”Emulation”).
2.2.6
Instruction Set
The MARC4 instruction set is optimized for the high level
programming
language
qFORTH.
Many
MARC4
instructions are qFORTH words. This enables the
compiler to generate a fast and compact program code.
The CPU has an instruction pipeline allowing the
controller to prefetch an instruction from ROM at the
same time as the present instruction is being executed.
The MARC4 is a zero address machine, the instructions
containing only the operation to be performed and no
source or destination address fields. The operations are
implicitly performed on the data placed on the stack.
There are one and two byte instructions which are
executed within 1 to 4 machine cycles. A MARC4
machine cycle is made up of two system clock
cycles (SYSCL). Most of the instructions are only one
byte long and are executed in a single machine cycle. For
more information refer to the ”MARC4 Programmer’s
Guide”.
2.2.7
Interrupt Structure
The MARC4 can handle interrupts with eight different
priority levels. They can be generated from the internal
and external interrupt sources or by a software interrupt
from the CPU itself. Each interrupt level has a hard-wired
priority and an associated vector for the service routine in
the ROM (see table 2). The programmer can postpone the
processing of interrupts by resetting the interrupt enable
flag (I) in the CCR. An interrupt occurrence will still be
registered, but the interrupt routine only started after the
I flag is set. All interrupts can be masked, and the priority
individually software configured by programming the
appropriate control register of the interrupting module.
(see section ”Peripheral Modules”).
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