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参数资料
| 型号： | M44C892 |
| 厂商： | ATMEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 4-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | SSO-20 |
| 文件页数： | 6/84页 |
| 文件大小： | 643K |
| 代理商： | M44C892 |
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M44C892
M44C092
Rev. A5, 14-Dec-01
14 (84)
A power-on reset pulse is generated by a VDD rise across
the default BOT voltage level (1.7 V). A brown-out reset
pulse is generated when VDD falls below the brown-out
voltage threshold. Two values for the brown-out voltage
threshold are programmable via the BOT-bit in the
SC-register. When the controller runs in the upper supply
voltage range with a high system clock frequency, the
high threshold must be used. When it runs with a lower
system clock frequency, the low threshold and a wider
supply voltage range may be chosen. For further details,
see the electrical specification and the SC-register
description for BOT programming.
2.3.2
Watchdog Reset
The watchdog’s function can be enabled at the WDC-reg-
ister and triggers a reset with every watchdog counter
overflow. To supress the watchdog reset, the watchdog
counter must be regularly reset by reading the watchdog
register address (CWD).
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
2.3.3
External Clock Supervisor
The external input clock supervisor function can be
enabled if the external input clock is selected within the
CM- and SC-registers of the clock module.
The CPU reacts in exactly the same manner as a reset
stimulus from any of the above sources.
2.4
Voltage Monitor
The voltage monitor consists of a comparator with
internal voltage reference. It is used to supervise the
supply voltage or an external voltage at the VMI-pin. The
comparator for the supply voltage has three internal
programmable thresholds one lower threshold (2.2 V),
one middle threshold (2.6 V). and one higher threshold
(3.0 V). For external voltages at the VMI-pin, the
comparator threshold is set to VBG = 1.3 V. The VMS-bit
indicates if the supervised voltage is below (VMS = 0) or
above (VMS = 1) this threshold. An interrupt can be
generated when the VMS-bit is set or reset to detect a
rising or falling slope. A voltage monitor interrupt (INT7)
is enabled when the interrupt mask bit (VIM) is reset in
the VMC-register.
V
DD
VM2
Voltage monitor
VM1 VM0 VIM
VMS
–
res
OUT
IN
BP41/
VMI
INT7
VMC :
VMST :
13754
Figure 11. Voltage monitor
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