参数资料
型号: M470L3224FT0-LA0
元件分类: DRAM
英文描述: 32M X 64 DDR DRAM MODULE, 0.75 ns, DMA200
封装: SODIMM-200
文件页数: 2/17页
文件大小: 308K
代理商: M470L3224FT0-LA0
DDR SDRAM
128MB, 256MB Unbuffered SODIMM
Rev. 1.3 July 2005
Output Load Circuit (SSTL_2)
Output
Z0=50
CLOAD=30pF
VREF
=0.5*VDDQ
RT=50
Vtt=0.5*VDDQ
( TA= 25
°C, f=100MHz)
Parameter
Symbol
M470L1624FT(U)0
M470L3224FT(U)0
Unit
Min
Max
Min
Max
Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE )
CIN1
41454957
pF
Input capacitance(CKE0,CKE1)
CIN2
34
38
42
50
pF
Input capacitance( CS0, CS1)
CIN3
34
38
42
50
pF
Input capacitance( CLK0, CLK1,CLK2)
CIN4
25
30
25
30
pF
Input capacitance(DM0~DM7)
CIN5
6
7
6
7
pF
Data & DQS input/output capacitance(DQ0~DQ63)
Cout1
6
7
6
7
pF
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on CK.
2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in
simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Parameter/Condition
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM signals
VIH(AC)
VREF + 0.31
V
3
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
VIL(AC)
VREF - 0.31
V
3
Input Differential Voltage, CK and CK inputs
VID(AC)
0.7
VDDQ+0.6
V
1
Input Crossing Point Voltage, CK and CK inputs
VIX(AC)
0.5*VDDQ-0.2
0.5*VDDQ+0.2
V
2
11.0 Input/Output Capacitance
10.0 AC Operating Conditions
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