参数资料
型号: M48T02-200PC1
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP24
封装: 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
文件页数: 2/25页
文件大小: 199K
代理商: M48T02-200PC1
Operation modes
M48T02, M48T12
Table 4.
Write mode AC characteristics
2.3
Data retention mode
With valid VCC applied, the M48T02/12 operates as a conventional BYTEWIDE static
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs
become high impedance, and all inputs are treated as “don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the
user can be assured the memory will be in a write protected state, provided the VCC fall time
is not less than tF. The M48T02/12 may respond to transient noise spikes on VCC that reach
into the deselect window during the time the device is sampling VCC. Therefore, decoupling
of the power supply lines is recommended.
The power switching circuit connects external VCC to the RAM and disconnects the battery
when VCC rises above VSO. As VCC rises, the battery voltage is checked. If the voltage is too
low, an internal battery not oK (BOK) flag will be set. The BOK flag can be checked after
power up. If the BOK flag is set, the first WRITE attempted will be blocked. The flag is
automatically cleared after the first WRITE, and normal RAM operation resumes. Figure 7
on page 11 illustrates how a BOK check routine could be structured.
For more information on a battery storage life refer to the application note AN1012.
Symbol
Parameter(1)
1.
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48T02/M48T12
Unit
–70
–150
–200
Min
Max
Min
Max
Min
Max
tAVAV
WRITE cycle time
70
150
200
ns
tAVWL
Address valid to WRITE enable low
0
ns
tAVEL
Address valid to chip enable low
0
ns
tWLWH
WRITE enable pulse width
50
90
120
ns
tELEH
Chip enable low to chip enable high
55
90
120
ns
tWHAX
WRITE enable high to address transition
0
10
ns
tEHAX
Chip enable high to address transition
0
10
ns
tDVWH
Input valid to WRITE enable high
30
40
60
ns
tDVEH
Input valid to chip enable high
30
40
60
ns
tWHDX
WRITE enable high to input transition
5
ns
tEHDX
Chip enable high to input transition
5
ns
tWLQZ
WRITE enable low to output Hi-Z
25
50
60
ns
tAVWH
Address valid to WRITE enable high
60
120
140
ns
tAVEH
Address valid to chip enable high
60
120
140
ns
tWHQX
WRITE enable high to output transition
5
10
ns
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