参数资料
型号: M48T08SH
厂商: 意法半导体
英文描述: 64 Kbit 8Kb x 8 TIMEKEEPER SRAM
中文描述: 64千位的8kB × 8计时器的SRAM
文件页数: 7/27页
文件大小: 398K
代理商: M48T08SH
7/27
M48T08, M48T08Y, M48T18
READ Mode
The M48T08/18/08Y is in the READ Mode when-
ever W (WRITE Enable) is high, E1 (Chip Enable
1) is low, and E2 (Chip Enable 2) is high. The de-
vice architecture allows ripple-through access of
data from eight of 65,536 locations in the static
storage array. Thus, the unique address specified
by the 13 address inputs defines which one of the
8,192 bytes of data is to be accessed. Valid data
will be available at the Data I/O pins within address
access time (t
AVQV
) after the last address input
signal is stable, providing that the E1, E2, and G
access times are also satisfied. If the E1, E2 and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
times (t
E1LQV
or t
E2HQV
) or Output Enable Access
time (t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E1, E2 and G. If the outputs are ac-
tivated before t
AVQV
, the data lines will be driven to
an indeterminate state until t
AVQV
. If the address
inputs are changed while E1, E2 and G remain ac-
tive, output data will remain valid for Output Data
Hold time (t
AXQX
) but will go indeterminate until the
next address access.
Figure 7. READ Mode AC Waveforms
Note: WRITE Enable (W) = High.
AI00962
tAVAV
tAVQV
tAXQX
tE1LQV
tE1LQX
tE1HQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A12
E1
G
DQ0-DQ7
tE2HQV
tE2HQX
VALID
tE2LQZ
E2
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