参数资料
型号: M48T212A-85MH6TR
厂商: 意法半导体
英文描述: 3.3V TIMEKEEPER CONTROLLER
中文描述: 3.3计时控制器
文件页数: 11/20页
文件大小: 165K
代理商: M48T212A-85MH6TR
11/20
M48T212A
The RST signal also remains active during this
time (see Figure 5).
Note:
Most low power SRAMs on the market to-
day can be used with the M48T212A TIMEKEEP-
ER Controller. There are, however some criteria
which should be used in making the final choice of
an SRAM to use. The SRAM must be designed in
a way where the chip enable input disables all oth-
er inputs to the SRAM. This allows inputs to the
M48T212A and SRAMs to be Don’t Care once
V
CC
falls below V
PFD
(min). The SRAM should also
guarantee data retention down to V
CC
= 2.0V. The
chip enable access time must be sufficient to meet
the system needs with the chip enable output
propagation delays included.
If the SRAM includes a second chip enable pin
(E2), this pin should be tied to V
OUT
.
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
The data retention current value of the SRAMs can
then be added to the I
BAT
value of the M48T212A
to determine the total current requirements for
data retention. The available battery capacity can
then be divided by this current to determine the
amount of data retention available.
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Table 13. TIMEKEEPER Register Map
Address
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
Fh
10 Years
Year
Year
00-99
Eh
0
0
0
10M
Month
Month
01-12
Dh
0
0
10 Date
Date: Day of Month
Date
01-31
Ch
0
FT
0
0
0
Day of Week
Day
01-7
Bh
0
0
10 Hours
Hours (24 Hour Format)
Hour
00-23
Ah
0
10 Minutes
Minutes
Min
00-59
9h
ST
10 Seconds
Seconds
Sec
00-59
8h
W
R
S
Calibration
Control
7h
WDS
BMB4
BMB3
BMB2
BMB1
BMB0
RB1
RB0
Watchdog
6h
AFE
0
ABE
Al 10M
Alarm Month
A Month
01-12
5h
RPT4
RPT5
AI 10 Date
Alarm Date
A Date
01-31
4h
RPT3
0
AI 10 Hour
Alarm Hour
A Hour
00-23
3h
RPT2
Alarm 10 Minutes
Alarm Minutes
A Min
00-59
2h
RPT1
Alarm 10 Seconds
Alarm Seconds
A Sec
00-59
1h
1000 Year
100 Year
Century
00-99
0h
WDF
AF
Y
BL
Y
Y
Y
Y
Flag
Keys:
S = Sign Bit
FT = Frequency Test Bit
R = Read Bit
W = Write Bit
ST = Stop Bit
0 = Must be set to zero
BL = Battery Low Flag
BMB0-BMB4 = Watchdog Multiplier Bits
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog flag
AF = Alarm flag
Y = ’1’ or ’0’
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