参数资料
型号: M48T212A-85MH6TR
厂商: 意法半导体
英文描述: 3.3V TIMEKEEPER CONTROLLER
中文描述: 3.3计时控制器
文件页数: 8/20页
文件大小: 165K
代理商: M48T212A-85MH6TR
M48T212A
8/20
Table 11. Write Mode AC Characteristics
(T
A
= 0 to 70°C)
Note: 1. C
L
= 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Symbol
Parameter
M48T212A
Unit
-85
Min
Max
t
AVAV
Write Cycle Time
85
ns
t
AVWL
Address Valid to Write Enable Low
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
ns
t
WLWH
Write Enable Pulse Width
55
ns
t
ELEH
Chip Enable Low to Chip Enable High
60
ns
t
WHAX
Write Enable High to Address Transition
0
ns
t
EHAX
Chip Enable High to Address Transition
0
ns
t
DVWH
Input Valid to Write Enable High
30
ns
t
DVEH
Input Valid to Chip Enable High
30
ns
t
WHDX
Write Enable High to Input Transition
0
ns
t
EHDX
Chip Enable High to Input Transition
0
ns
t
WLQZ
(1,2)
Write Enable Low to Output High-Z
25
ns
t
AVWH
Address Valid to Write Enable High
65
ns
t
AVEH
Address Valid to Chip Enable High
65
ns
t
WHQX
(1,2)
Write Enable High to Output Transition
5
ns
Address Decoding
The M48T212A accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the controller chip itself. All
TIMEKEEPER registers are accessed by enabling
E (Chip Enable).
READ MODE
The M48T212A executes a read cycle whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the address
inputs (A3-A0) defines which one of the on-chip
TIMEKEEPER registers is to be accessed. When
the address presented to the M48T212A is in the
range of 0h-Fh, one of the on-board TIMEKEEP-
ER registers is accessed and valid data will be
available to the eight data output drivers within
t
AVQV
after the address input signal is stable, pro-
viding that the E and G access times are also sat-
isfied. If they are not, then data access must be
measured from the latter occurring signal (E or G)
and the limiting parameter is either t
ELQV
for E or
t
GLQV
for G rather than the address access time.
When EX input is low, an external SRAM location
will be selected.
Note:
Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
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