参数资料
型号: M48T212V-85MH1E
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDSO44
封装: 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-44
文件页数: 13/35页
文件大小: 348K
代理商: M48T212V-85MH1E
Obsolete
Product(s)
- Obsolete
Product(s)
Clock operation
M48T212V
Figure 8.
Back-up mode alarm waveforms
3.6
Watchdog timer
The watchdog timer can be used to detect an out-of-control microprocessor. The user
programs the watchdog timer by setting the desired amount of time-out into the Watchdog
Register, address 7h.
Bits BMB4-BMB0 store a binary multiplier and the two lower-order bits RB1-RB0 select the
resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The
amount of time-out is then determined to be the multiplication of the five-bit multiplier value
with the resolution. (For example: writing 00001110 in the Watchdog Register = 3*1 or 3
seconds).
Note:
Accuracy of timer is within ± the selected resolution.
If the processor does not reset the timer within the specified period, the M48T212V sets the
WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. WDF
is reset by reading the Flags Register (Address 0h).
The most significant bit of the Watchdog Register is the Watchdog Steering Bit (WDS).
When set to a '0.' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is
set to a '1,' the watchdog will output a negative pulse on the RST pin for 40 to 200 ms. The
Watchdog register, AFE, ABE, and FT Bits will reset to a '0' at the end of a Watchdog time-
out when the WDS Bit is set to a '1.'
The watchdog timer can be reset by two methods:
1.
a transition (high-to-low or low-to-high) can be applied to the Watchdog Input pin (WDI)
or
2.
the microprocessor can perform a WRITE of the Watchdog Register.
The time-out period then starts over. The WDI pin should be tied to VSS if not used. The
watchdog will be reset on each transition (edge) seen by the WDI pin. In the order to
AI03622
VCC
IRQ/FT
HIGH-Z
VPFD (max)
VPFD (min)
AFE Bit/ABE Bit
AF Bit in Flags Register
HIGH-Z
tREC
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