参数资料
型号: M48T212V-85MH1E
厂商: STMICROELECTRONICS
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDSO44
封装: 0.330 INCH, ROHS COMPLIANT, PLASTIC, SOH-44
文件页数: 3/35页
文件大小: 348K
代理商: M48T212V-85MH1E
Obsolete
Product(s)
- Obsolete
Product(s)
M48T212V
Operation
Table 4.
Chip enable control and bank select characteristics
2.2
Read mode
The M48T212V executes a READ cycle whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The unique address specified by the address inputs (A3-A0) defines which
one of the on-chip TIMEKEEPER registers is to be accessed. When the address
presented to the M48T212V is in the range of 0h-Fh, one of the on-board TIMEKEEPER
registers is accessed and valid data will be available to the eight data output drivers within
tAVQV after the address input signal is stable, providing that the E and G access times are
also satisfied.If they are not, then data access must be measured from the latter occurring
signal (E or G) and the limiting parameter is either tELQV for E or tGLQV for G rather than the
address access time.
When EX input is low, an external SRAM location will be selected.
Note:
Care should be taken to avoid taking both E and EX low simultaneously to avoid bus
contention.
Figure 5.
Read cycle timing: RTC control signal waveforms
Note:
EX is assumed high.
Symbol
Parameter
M48T212V
Unit
–85
Min
Max
tEXPD
EX to E1CON or E2CON (low or high)
15
ns
tAPD
A to E1CON or E2CON (low or high)
15
ns
AI02640
W
DQ7-DQ0
G
DATA OUT
VALID
ADDRESS
tAVAV
E
tELQV
tAVAV
READ
WRITE
DATA IN
VALID
DATA OUT
VALID
tAVQV
tWHAX
tAVWL
tELQX
tGLQV
tGHQZ
tWLWH
tAXQX
tGLQX
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