参数资料
型号: M4LV-96/48-12VI
厂商: LATTICE SEMICONDUCTOR CORP
元件分类: PLD
英文描述: High Performance E 2 CMOS In-System Programmable Logic
中文描述: EE PLD, 12 ns, PQFP100
封装: TQFP-100
文件页数: 14/46页
文件大小: 754K
代理商: M4LV-96/48-12VI
MACH 4 Family
21
POWER MANAGEMENT
Each individual PAL block in MACH 4 devices features a programmable low-power mode, which
results in power savings of up to 50%. The signal speed paths in the low-power PAL block will
be slower than those in the non-low-power PAL block. This feature allows speed critical paths
to run at maximum frequency while the rest of the signal paths operate in the low-power mode.
PROGRAMMABLE SLEW RATE
Each MACH 4 device I/O has an individually programmable output slew rate control bit. Each
output can be individually congured for the higher speed transition (3 V/ns) or for the lower
noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew
rate will introduce fewer reections, less noise, and keep ground bounce to a minimum. For
designs with short traces or well terminated lines, the fast slew rate can be used to achieve the
highest speed. The slew rate is adjusted independent of power.
POWER-UP RESET/SET
All ip-ops power up to a known state for predictable system initialization. If a macrocell is
congured to SET on a signal from the control generator, then that macrocell will be SET during
device power-up. If a macrocell is congured to RESET on a signal from the control generator
or is not congured for set/reset, then that macrocell will RESET on power-up. To guarantee
initialization values, the VCC rise must be monotonic, and the clock must be inactive until the
reset delay time has elapsed.
SECURITY BIT
A programmable security bit is provided on the MACH 4 devices as a deterrent to unauthorized
copying of the array conguration patterns. Once programmed, this bit defeats readback of the
programmed pattern by a device programmer, securing proprietary designs from competitors.
Programming and verication are also defeated by the security bit. The bit can only be reset by
erasing the entire device.
相关PDF资料
PDF描述
M4LV-96/48-15VC High Performance E 2 CMOS In-System Programmable Logic
M4LV-96/48-18VI High Performance E 2 CMOS In-System Programmable Logic
M4LV-96/48-7VC High Performance E 2 CMOS In-System Programmable Logic
M4LV-256/128-10YI High Performance E 2 CMOS In-System Programmable Logic
M4LV-64/32-18VI High Performance E 2 CMOS In-System Programmable Logic
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