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参数资料
| 型号： | M58BW016DB90ZA3FT |
| 厂商： | NUMONYX |
| 元件分类： | PROM |
| 英文描述： | 512K X 32 FLASH 3V PROM, 90 ns, PBGA80 |
| 封装： | 10 X 12 MM, 1 MM PITCH, LBGA-80 |
| 文件页数： | 7/63页 |
| 文件大小： | 901K |
| 代理商： | M58BW016DB90ZA3FT |
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BUS OPERATIONS
Each bus operations that controls the memory is
Bus Operations, for a summary. The bus operation
is selected through the Burst Configuration Regis-
ter; the bits in this register are described at the end
of this section.
On Power-up or after a Hardware Reset the mem-
ory defaults to Asynchronous Bus Read and Asyn-
chronous Bus Write, no other bus operation can
be performed until the Burst Control Register has
been configured.
The Electronic Signature, CFI or Status Register
will be read in asynchronous mode regardless of
the Burst Control Register settings.
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Asynchronous Bus Operations
For asynchronous bus operations refer to Table 4
together with the following text.
Asynchronous Bus Read. Asynchronous
Bus
Read operations read from the memory cells, or
specific registers (Electronic Signature, Status
Register, CFI and Burst Configuration Register) in
the Command Interface. A valid bus operation in-
volves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable
and Output Enable and keeping Write Enable and
Output Disable High, VIH. The Data Inputs/Out-
puts will output the value, see Figure 9, Asynchro-
nous Bus Read AC Waveforms, and Table 16,
Asynchronous Bus Read AC Characteristics, for
details of when the output becomes valid.
Asynchronous Read is the default read mode
which the device enters on power-up or on return
from Reset/Power-Down.
Asynchronous Latch Controlled Bus Read.
Asynchronous Latch Controlled Bus Read opera-
tions read from the memory cells or specific regis-
ters in the Command Interface. The address is
latched in the memory before the value is output
on the data bus, allowing the address to change
during the cycle without affecting the address that
the memory uses.
A valid bus operation involves setting the desired
address on the Address Inputs, setting Chip En-
able and Latch Enable Low, VIL and keeping Write
Enable High, VIH; the address is latched on the ris-
ing edge of Latch Enable. Once latched, the Ad-
dress Inputs can change. Set Output Enable Low,
VIL, to read the data on the Data Inputs/Outputs;
see Figure 1, Asynchronous Latch Controlled Bus
Read AC Waveforms and Table 17, Asynchro-
nous Latch Controlled Bus Read AC Characteris-
tics for details on when the output becomes valid.
Note that, since the Latch Enable input is transpar-
ent when set Low, VIL, Asynchronous Bus Read
operations can be performed when the memory is
configured for Asynchronous Latch Enable bus
operations by holding Latch Enable Low, VIL
throughout the bus operation.
Asynchronous Page Read. Asynchronous
Page Read operations are used to read from sev-
eral addresses within the same memory page.
Each memory page is 4 Double-Words and is ad-
dressed by the address inputs A0 and A1.
Data is read internally and stored in the Page Buff-
er. Valid bus operations are the same as Asyn-
chronous Bus Read operations but with different
timings. The first read operation within the page
has identical timings, subsequent reads within the
same page have much shorter access times. If the
page changes then the normal, longer timings ap-
ply again. Page Read does not support Latched
Controlled Read.
See Figure 11, Asynchronous Page Read AC
Waveforms and Table 18, Asynchronous Page
Read AC Characteristics for details on when the
outputs become valid.
Asynchronous Bus Write. Asynchronous
Bus
Write operations write to the Command Interface
in order to send commands to the memory or to
latch addresses and input data to program. Bus
Write operations are asynchronous, the clock, K,
is don’t care during Bus Write operations.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts, and setting Chip Enable, Write Enable and
Latch Enable Low, VIL, and Output Enable High,
VIH, or Output Disable Low, VIL. The Address In-
puts are latched by the Command Interface on the
rising edge of Chip Enable or Write Enable, which-
ever occurs first. Commands and Input Data are
latched on the rising edge of Chip Enable, E, or
Write Enable, W, whichever occurs first. Output
Enable must remain High, and Output Disable
Low, during the whole Asynchronous Bus Write
operation.
See Figure 12, Asynchronous Write AC Wave-
forms, and Table 19, Asynchronous Write and
Latch Controlled Write AC Characteristics, for de-
tails of the timing requirements.
Asynchronous Latch Controlled Bus Write.
Asynchronous Latch Controlled Bus Write opera-
tions write to the Command Interface in order to
send commands to the memory or to latch ad-
dresses and input data to program. Bus Write op-
erations are asynchronous, the clock, K, is don’t
care during Bus Write operations.
A valid Asynchronous Latch Controlled Bus Write
operation begins by setting the desired address on
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| M58LW032A | 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M58BW016DB90ZA3T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DB90ZA6T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DBT | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DBZA | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:16 Mbit 512Kb x32, Boot Block, Burst 3V Supply Flash Memories |
| M58BW016DT | 制造商:NUMONYX 制造商全称:Numonyx B.V 功能描述:16 Mbit (512 Kbit x 32, boot block, burst) 3 V supply Flash memories |
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