参数资料
型号: M58LW064D11N1T
厂商: STMICROELECTRONICS
元件分类: PROM
英文描述: 4M X 16 FLASH 3V PROM, 110 ns, PDSO56
封装: 14 X 20 MM, PLASTIC, TSOP-56
文件页数: 45/50页
文件大小: 280K
代理商: M58LW064D11N1T
5/50
M58LW064D
SUMMARY DESCRIPTION
The M58LW064D is a 64 Mbit (8Mb x 8 or 4Mb
x16) non-volatile memory that can be read, erased
and reprogrammed. These operations can be per-
formed using a single low voltage (2.7V to 3.6V)
core supply.
The memory is divided into 64 blocks of 1Mbit that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller simplifies the process of
programming or erasing the memory by taking
care of all of the special operations that are re-
quired to update the memory contents. The end of
a Program or Erase operation can be detected and
any error conditions identified in the Status Regis-
ter. The command set required to control the
memory is consistent with JEDEC standards.
The Write Buffer allows the microprocessor to pro-
gram from 1 to 16 Words in parallel, both speeding
up the programming and freeing up the micropro-
cessor to perform other work. A Word Program
command is available to program a single word.
Erase can be suspended in order to perform either
Read or Program in any other block and then re-
sumed. Program can be suspended to Read data
in any other block and then resumed. Each block
can be programmed and erased over 100,000 cy-
cles.
Individual block protection against Program or
Erase is provided for data security. All blocks are
protected during power-up. The protection of the
blocks is non-volatile; after power-up the protec-
tion status of each block is restored to the state
when power was last removed. Software com-
mands are provided to allow protection of some or
all of the blocks and to cancel all block protection
bits simultaneously. All Program or Erase opera-
tions are blocked when the Program Erase Enable
input VPEN is low.
The Reset/Power-Down pin is used to apply a
Hardware Reset to the memory and to set the de-
vice in power-down mode.
The STS pin gives information about the memory
status. It can be configured in two status: to output
a static signal about the status of P/E C (when low
P/E C is busy, when high P/E C is ready for a new
operation) or to give a pulsing signal to indicate
the end of programming or erasing blocks. In this
last configuration it supplies a system interrupt sig-
nal useful for saving time
The Bus operations of the device are controlled by
Output Enable, Write Enable and three different
Chip Enables. Refer to Table 2, Device Enable, for
all possible combinations to enable and disable
the device. Together they allow simple, yet power-
ful, connection to most microprocessor, often with-
out additional logic.
The device includes a 128 bit Protection Register.
The Protection Register is divided into two 64 bit
segments, the first one is written by the manufac-
turer (contact STMicroelectronics to define the
code to be written here), while the second one is
programmable by the user. The user programma-
ble segment can be locked.
The memory is available in TSOP56 (14 x 20 mm)
and TBGA64 (10x13mm, 1mm pitch) packages.
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