参数资料
型号: M68Z128W-70N1T
厂商: 意法半导体
英文描述: 3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable
中文描述: 3V的,1兆位的输出128KB的x8低功耗SRAM启用
文件页数: 5/12页
文件大小: 96K
代理商: M68Z128W-70N1T
5/12
M68Z128W
Figure 5. Address Controlled, Read Mode AC Waveforms
Note: E1 = Low, E2 = High, G = Low, W = High.
AI01078
tAVAV
tAVQV
tAXQX
A0-A16
DQ0-DQ7
VALID
DATA VALID
Table 7. Read and Standby Modes AC Characteristics
(
T
A
= 0 to 70°C; V
CC
= 3.0V + 0.6V / –0.3V)
Note: 1. C
L
= 50pF (see Figure 3).
2. C
L
= 5pF (see Figure 3).
3. At any given temperature and voltage condition, t
EIHQZ
+ t
EZHQZ
is less than t
EILQX
and t
EZLQX
, t
GHQZ
is less than t
GLQX
for any
given device.
Symbol
Parameter
M68Z128W
Unit
-70
Min
Max
t
AVAV
Read Cycle Time
70
ns
t
AVQV(1)
Address Valid to Output Valid
70
ns
t
E1LQV
(1)
Chip Enable 1 Low to Output Valid
70
ns
t
E2HQV
(1)
Chip Enable 2 High to Output Valid
70
ns
t
GLQV
(1)
Output Enable Low to Output Valid
35
ns
t
E1LQX
(3)
Chip Enable 1 Low to Output Transition
10
ns
t
E2HQX
(3)
Chip Enable 2 High to Output Transition
10
ns
t
GLQX
(3)
Output Enable Low to Output Transition
10
ns
t
E1HQZ
(2,3)
Chip Enable 1 High to Output Hi-Z
0
25
ns
t
E2LQZ
(2,3)
Chip Enable 2 Low to Output Hi-Z
0
25
ns
t
GHQZ
(2,3)
Output Enable High to Output Hi-Z
0
25
ns
t
AXQX
(1)
Address Transition to Output Transition
10
ns
t
PU
Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
t
PD
Chip Enable 1 High or Chip Enable 2 Low to Power Down
70
ns
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