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参数资料
| 型号： | M68Z128WN |
| 厂商： | 意法半导体 |
| 英文描述： | 3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| 中文描述： | 3V的，1兆位的输出128KB的x8低功耗SRAM启用 |
| 文件页数： | 1/12页 |
| 文件大小： | 96K |
| 代理商： | M68Z128WN |
1/12
March 2000
M68Z128W
3V, 1 Mbit (128Kb x8) Low Power SRAM with Output Enable
I
LOW VOLTAGE: 3.0V (+0.6V / –0.3V)
I
128Kb x 8 LOW POWER SRAM with OUTPUT
ENABLE
I
EQUAL CYCLE and ACCESS TIMES: 70ns
I
LOW V
CC
DATA RETENTION: 1.4V
I
TRI-STATE COMMON I/O
I
LOW ACTIVE and STANDBY POWER
I
INTENDED for USE with ST ZEROPOWER
and TIMEKEEPER
CONTROLLERS
DESCRIPTION
The M68Z128W is a 1 Mbit (1,048,576 bit) Fast
CMOS SRAM, organized as 131,072 words by 8
bits. The device features fully static operation re-
quiring no external clocks or timing strobes, with
equal address access and cycle times. It requires
a single 3.0V (+0.6V / –0.3V) supply, and all inputs
and outputs are TTL compatible. This device has
an automatic power-down feature, reducing the
power consumption by over 99% when deselect-
ed. The M68Z128W is available in the standard
450mil-wide TSOP type 1 package.
Figure 1. Logic Diagram
AI01878B
17
A0-A16
W
DQ0-DQ7
VCC
M68Z128W
G
E2
VSS
8
E1
TSOP32 (N)
8 x 20mm
Table 1. Signal Names
A0-A16
Address Inputs
DQ0-DQ7
Data Input/Output
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
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