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参数资料
| 型号： | M68Z128WN |
| 厂商： | 意法半导体 |
| 英文描述： | 3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| 中文描述： | 3V的，1兆位的输出128KB的x8低功耗SRAM启用 |
| 文件页数： | 7/12页 |
| 文件大小： | 96K |
| 代理商： | M68Z128WN |
7/12
M68Z128W
Table 8. Write Mode AC Characteristics
(T
A
= 0 to 70°C; V
CC
= 3.0V + 0.6V / –0.3V)
Note: 1. C
L
= 5pF.
2. At any given temperature and voltage condition, t
WHQX
is less than t
WLQZ
for any given device.
Symbol
Parameter
M68Z128W
Unit
-70
Min
Max
t
AVAV
Write Cycle Time
70
ns
t
AVWL
Address Valid to Write Enable Low
0
ns
t
AVWH
Address Valid to Write Enable High
60
ns
t
AVE1H
Address Valid to Chip Enable 1 High
60
ns
t
AVE2L
Address Valid to Chip Enable 2 Low
60
ns
t
WLWH
Write Enable Pulse Width
55
ns
t
WHAX
Write Enable High to Address Transition
0
ns
t
WHDX
Write Enable High to Input Transition
0
ns
t
WHQX (2)
Write Enable High to Output Transition
0
ns
t
WLQZ (1,2)
Write Enable Low to Output Hi-Z
25
ns
t
AVE1L
Address Valid to Chip Enable 1 Low
0
ns
t
AVE2H
Address Valid to Chip Enable 2 High
0
ns
t
E1LE1H
Chip Enable 1 Low to Chip Enable 1 High
60
ns
t
E2HE2L
Chip Enable 2 High to Chip Enable 2 Low
60
ns
t
E1HAX
Chip Enable 1 High to Address Transition
0
ns
t
E2LAX
Chip Enable 2 Low to Address Transition
0
ns
t
DVWH
Input Valid to Write Enable High
30
ns
t
DVE1H
Input Valid to Chip Enable 1 High
30
ns
t
DVE2L
Input Valid to Chip Enable 2 Low
30
ns
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