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参数资料
| 型号： | M68Z128WN |
| 厂商： | 意法半导体 |
| 英文描述： | 3V, 1 Mbit 128Kb x8 Low Power SRAM with Output Enable |
| 中文描述： | 3V的，1兆位的输出128KB的x8低功耗SRAM启用 |
| 文件页数： | 4/12页 |
| 文件大小： | 96K |
| 代理商： | M68Z128WN |
M68Z128W
4/12
Figure 4. Block Diagram
AI00665
ROW
DECODER
A
A
(9)
CHIP ENABLE.
INPUT
DATA
CTRL
DQ
DQ
(8)
COLUMN
DECODER
I/O CIRCUITS
(8)
A
A
CHIP ENABLE.
E1
W
G
CHIP
ENABLE
MEMORY
ARRAY
VCC
VSS
E2
Table 6. DC Characteristics
(T
A
= 0 to 70°C; V
CC
= 3.0V + 0.6V / –0.3V)
Symbol
Parameter
I
LI
Input Leakage Current
I
LO
Output Leakage Current
I
CC1 (1)
Supply Current
Note: 1. Average AC current, Outputs open, cycling at t
AVAV
minimum.
2. All other Inputs at V
IL
≤
0.8V or V
IH
≥
2.0V.
3. All other Inputs at V
IL
≤
0.2V or V
IH
≥
V
CC
–0.2V.
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
V
CC
= 3.6V, (-70)
V
CC
= 3.6V, E1 = V
IH
or
E2 = V
IL
, f =0
V
CC
= 3.6V, E1
≥
V
CC
– 0.2V
or E2
≤
0.2V, f =0
Min
Typ
Max
±1
±1
Unit
μA
μA
20
40
mA
I
CC2 (2)
Supply Current (Standby) TTL
15
300
μA
I
CC3 (3)
Supply Current (Standby) CMOS
0.4
15
μA
V
IL
V
IH
V
OL
V
OH
Input Low Voltage
–0.5
0.8
V
Input High Voltage
Output Low Voltage
Output High Voltage
2
V
CC
+ 0.5
0.4
V
V
V
I
OL
= 2.1mA
I
OH
= –1mA
2.4
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