参数资料
型号: M69AW024BE
厂商: 意法半导体
英文描述: 16 Mbit (1M x16) 3V Asynchronous PSRAM
中文描述: 16兆位(1米× 16)3V的异步移动存储芯片
文件页数: 13/25页
文件大小: 147K
代理商: M69AW024BE
13/25
M69AW024BE
Table 7. Read and Standby Modes AC Characteristics
Note: 1. The maximum value of this timing is applicable if E1 is kept Low with addresses unchanged.If needed by the system operation,
please contact your local ST representative for relaxation of the 1000ns limitation.
2. Addresses should not be changed during t
AVAX
(min).
3. These parameters are measured according to the conditions on input and output timing reference voltage shown on
Figure 6., AC
Measurement I/O Waveform
.
4. The output load capacitance is 5pF without any other load.
5. These timings are given for E1 Low.
6. t
AVAX
(min) must be satisfied.
7. If the current value of t
WHGL
is lower than the minimum value given in the above table, t
AVQV
during the following Read operation
may increase by t
WHGL
(current)
t
WHGL
(min).
8. All timings are measured according to the conditions for output transition timing reference voltage shown on
Figure 6., AC Mea-
surement I/O Waveform
.
Symbol
Alt.
Parameter
M69AW024BE
Unit
–60
Min
Max
t
AVAX,
t
ELEH
(1,2)
t
RC
Read Cycle Time
70
1000
ns
t
ELQV(3)
t
CE
Chip Enable Access Time
60
ns
t
GLQV(3)
t
OE
Output Enable Access Time
40
ns
t
AVQV(3,5)
t
AA
Address Access Time
60
ns
t
BLQV(3)
t
BA
LB, UB Low to Output Valid
30
ns
t
AXQX,
t
GHQX,
t
BHQX
, t
EHQX
(8)
t
OH
Output Hold Time after Chip Enable Low
5
ns
t
ELQX(4,8)
t
CLZ
Chip Enable Low to Output Low-Z
5
ns
t
GLQX(4,8)
t
OLZ
Output Enable Low to Output Low-Z
0
ns
t
BLQX(4,8)
t
BLZ
LB, UB Low to Output Low-Z
0
ns
t
EHQZ(8)
t
CHZ
Chip Enable High to Output Hi-Z
20
ns
t
GHQZ(8)
t
OHZ
Output Enable High to Output Hi-Z
20
ns
t
BHQZ(8)
t
BHZ
LB, UB High to Output Hi-Z
20
ns
t
AVEL
t
ASC
Address Set-up Time to Chip Enable Low
–5
ns
t
AVGL
t
ASO
Address Valid to Output Enable Low
10
ns
t
AXAV(5)
t
AX
Address Invalid Time
10
ns
t
EHAX(6)
t
CHAH
Chip Enable High to Address Hold Time
–5
ns
t
GHAX
t
OHAH
Output Enable High to Address Hold Time
–5
ns
t
WHGL(7)
t
WHOL
Write Enable High to Output Enable Low (Read Operations)
10
1000
ns
t
EHEL
t
CP
Chip Enable High Pulse Width
10
ns
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